Method and structure for forming vertical transistors with various gate lengths
Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same.
1. A semiconductor structure comprising:
a first vertical fin field-effect transistor formed on a semiconductor substrate, the first vertical fin field-effect transistor comprising a first vertical fin, a first bottom source/drain junction layer disposed on the semiconductor substrate and a first gate disposed on the first bottom source/drain junction layer, the first gate having a first gate length; and
a second vertical fin field-effect transistor formed on the semiconductor substrate, the second vertical fin field-effect transistor comprising a second vertical fin, a second bottom source/drain junction layer disposed on the semiconductor substrate and a second gate disposed on the second bottom source/drain junction layer, the second gate having a second gate length that is greater than the first gate length, the first vertical fin including a staircase feature inside the first bottom source/drain junction layer and the second vertical fin does not include a staircase feature inside the second bottom source/drain junction layer.
2. The semiconductor structure of claim 1 , wherein the staircase feature includes a step from a vertically lower portion of the first vertical fin to a vertically higher portion of the first vertical fin.
3. The semiconductor structure of claim 2 , wherein the vertically lower portion of the first vertical fin in the staircase feature has a first horizontal width and the vertically higher portion of the first vertical fin in the staircase feature has a second horizontal width, the first horizontal width being greater than the second horizontal width.
4. The semiconductor structure of claim 1 , wherein the first bottom source/drain junction layer has a first height extending vertically upwards along the first vertical fin from a top surface of the semiconductor substrate, and the second bottom source/drain junction layer has a second height extending vertically upwards along the second vertical fin from a top surface of the semiconductor substrate, the first height being substantially the same as the second height.
5. An integrated circuit comprising:
a circuit supporting substrate; and
a semiconductor structure, the semiconductor structure comprising:
a first vertical fin field-effect transistor formed on a semiconductor substrate, the first vertical fin field-effect transistor comprising a first vertical fin, a first bottom source/drain junction layer disposed on the semiconductor substrate and a first gate disposed on the first bottom source/drain junction layer, the first gate having a first gate length; and
a second vertical fin field-effect transistor formed on the semiconductor substrate, the second vertical fin field-effect transistor comprising a second vertical fin, a second bottom source/drain junction layer disposed on the semiconductor substrate and a second gate disposed on the second bottom source/drain junction layer, the second gate having a second gate length that is greater than the first gate length, the first vertical fin including a staircase feature inside the first bottom source/drain junction layer and the second vertical fin does not include a staircase feature inside the second bottom source/drain junction layer.
6. The integrated circuit of claim 5 , wherein the staircase feature includes a step from a vertically lower portion of the first vertical fin to a vertically higher portion of the first vertical fin.
7. The integrated circuit of claim 6 , wherein the vertically lower portion of the first vertical fin in the staircase feature has a first horizontal width and the vertically higher portion of the first vertical fin in the staircase feature has a second horizontal width, the first horizontal width being greater than the second horizontal width.
8. The integrated circuit of claim 5 , wherein the first bottom source/drain junction layer has a first height extending vertically upwards along the first vertical fin from a top surface of the semiconductor substrate, and the second bottom source/drain junction layer has a second height extending vertically upwards along the second vertical fin from a top surface of the semiconductor substrate, the first height being substantially the same as the second height.
9. A semiconductor structure comprising:
a semiconductor substrate;
a first vertical fin field-effect transistor formed on the semiconductor substrate, the first vertical fin field-effect transistor comprising a first vertical fin, a first bottom source/drain junction layer disposed on the semiconductor substrate and a first gate, including a first high-k gate dielectric and a first gate conductor, disposed on the first bottom source/drain junction layer, the first gate having a first gate length vertically along the first vertical fin; and
a second vertical fin field-effect transistor formed on the semiconductor substrate, the second vertical fin field-effect transistor comprising a second vertical fin, a second bottom source/drain junction layer disposed on the semiconductor substrate and a second gate, including a second high-k gate dielectric and a second gate conductor, disposed on the second bottom source/drain junction layer, the second gate having a second gate length vertically along the second vertical fin that is greater than the first gate length, the first vertical fin including a staircase feature inside the first bottom source/drain junction layer and the second vertical fin does not include a staircase feature inside the second bottom source/drain junction layer.
10. The semiconductor structure of claim 9 , wherein the staircase feature includes a step from a vertically lower portion of the first vertical fin to a vertically higher portion of the first vertical fin.
11. The semiconductor structure of claim 10 , wherein the vertically lower portion of the first vertical fin in the staircase feature has a first horizontal width and the vertically higher portion of the first vertical fin in the staircase feature has a second horizontal width, the first horizontal width being greater than the second horizontal width.
12. The semiconductor structure of claim 9 , wherein the first bottom source/drain junction layer has a first height extending vertically upwards along the first vertical fin from a top surface of the semiconductor substrate, and the second bottom source/drain junction layer has a second height extending vertically upwards along the second vertical fin from a top surface of the semiconductor substrate, the first height being substantially the same as the second height.
13. The method of claim 12 , wherein a difference between the first height and the second height is less than one nanometer.
14. The semiconductor structure of claim 9 , wherein each of the first bottom source/drain layer and the second bottom source/drain layer comprises:
one of an nFET source/drain or a pFET source/drain.
15. The semiconductor structure of claim 9 , wherein a difference between the first gate length and the second gate length is in a range from two nanometers up to five nanometers.