IP Library Granted Patent US 10,916,169
Granted Patent B2
US 10,916,169 · App. 16/436,126 · Granted Feb 9, 2021

Pixel circuit having in-pixel compensation function

Inventors: Chih-Lung Lin (Hsin-Chu, TW); Chin-Hsien Tseng (Hsin-Chu, TW); Po-Cheng Lai (Hsin-Chu, TW); Yu-Sheng Lin (Hsin-Chu, TW); Mao-Hsun Cheng (Hsin-Chu, TW)
Assignee: AU OPTRONICS CORPORATION
G09G3/20G09G2300/043G09G2300/0426G09G2300/0809
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Quick Facts
Patent No.
US 10,916,169
App. No.
16/436,126
Granted
Feb 9, 2021
Kind
B2
Abstract

A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.

Claims (17)

1. A pixel circuit, comprising:

a light emitting element;

a first driver transistor comprising a first terminal, a second terminal and a control terminal, wherein the second terminal of the first driving transistor is electrically connected to the light emitting element;

a second driver transistor comprising a first terminal, a second terminal and a control terminal, wherein the control terminal of the second driving transistor is electrically connected to the light emitting element; and

a first compensation capacitor electrically connected to the control terminal of the first driving transistor and the second terminal of the second driving transistor, and a compensation node between the first compensation capacitor and the second driving transistor;

wherein the control terminal of the first driver transistor is configured to receive a data signal in a data input period;

wherein a voltage of the compensation node is substantially twice a voltage of the control terminal of the second driving transistor in a compensation period.

2. The pixel circuit of claim 1 , wherein when in a reset period, the first driver transistor is turned on, the first terminal of the first driver transistor is configured to receive a low voltage signal, and the second driver transistor is turned on.

3. The pixel circuit of claim 2 , wherein when in the reset period, a voltage of the compensation node is discharged to a sum of a threshold voltage value of the first driving transistor and a threshold voltage value of the second driving transistor.

4. The pixel circuit of claim 1 , further comprising:

a second compensation capacitor respectively electrically connected to the control terminal of the first driver transistor and a reference voltage source, wherein when in a data input period, the first driver transistor is turned off, and the first compensation capacitor and the second compensation capacitor change a voltage value of the compensation node according to the Capacitive coupling effect in order to turn on the second driver transistor.

5. The pixel circuit of claim 4 , wherein when in the compensation period, both of the first driver transistor and the second driver transistor are turned on, and a voltage value of the control terminal of the first driver transistor is decreased corresponding to a voltage change of the compensation node according to the capacitive coupling effect between the first compensation capacitor and the second compensation capacitor.

6. The pixel circuit of claim 1 , further comprising:

a transistor switch comprising a first terminal, a second terminal and a control terminal, wherein in the data input period, the first terminal of the transistor switch is configured to receive a data signal, the second terminal of the transistor switch is electrically connected to the control terminal of the first driving transistor.

7. The pixel circuit of claim 6 , wherein in a reset period, the transistor switch is turn on.

8. The pixel circuit of claim 7 , wherein in a lighting period, both of the first driver transistor and the second driver transistor are turned on, and the transistor switch is turned off.

9. The pixel circuit of claim 8 , wherein the reset period, the data input period, the compensation period, and the lighting period are sequentially arranged.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2019
From: LIN, CHIH-LUNG; TSENG, CHIN-HSIEN; LAI, PO-CHENG; LIN, YU-SHENG; CHENG, MAO-HSUN
To: AU OPTRONICS CORPORATION
Reel/Frame 049420/0553 →
Priority Claims (1)
TW 108100427 A · Jan 4, 2019 · national
Continuity (2)
Provisional Application 62684913 · Jun 14, 2018
Related Publication 20190385503A1 · Dec 19, 2019