IP Library › Granted Patent US 10,916,506
Granted Patent B2
US 10,916,506 · App. 16/355,917 · Granted Feb 9, 2021

Semiconductor device

Inventors: Youichi Ashida (Kariya, JP); Tsuyoshi Fujiwara (Kariya, JP)
Assignee: DENSO CORPORATION
H01L23/5329H01L21/3205H01L21/768H01L23/522H01L23/5226H01L23/5227H01L23/5283
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,916,506
App. No.
16/355,917
Granted
Feb 9, 2021
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate, an interlayer dielectric film, a plurality of pad parts, a wiring layer, and a surface protection film. The semiconductor substrate includes a semiconductor element on a surface of the semiconductor substrate. The interlayer dielectric film is disposed on the surface of the semiconductor substrate. The wiring layer is disposed in the interlayer dielectric film. The hard film is disposed opposite to the semiconductor substrate with respect to the interlayer dielectric film, and is harder than the interlayer dielectric film. The pad parts are disposed opposite to the interlayer dielectric film with respect to the hard film. The surface protection film is disposed in at least an opposing region where the pad parts oppose to each other. The surface protection film is a silicon nitride film or a silicon oxide film.

Claims (40)

1. A semiconductor device comprising:

a semiconductor substrate that includes a semiconductor element disposed on a surface of the semiconductor substrate;

an interlayer dielectric film that is disposed on the surface of the semiconductor substrate;

a wiring layer that is disposed in the interlayer dielectric film;

a hard film that is disposed opposite to the semiconductor substrate with respect to the interlayer dielectric film and that is harder than the interlayer dielectric film;

a plurality of pad parts for external connection that are disposed opposite to the interlayer dielectric film with respect to the hard film and that are connected via the wiring layer to the semiconductor element, the plurality of pad parts including a first pad part connected to a ground and a second pad part connected to an inductive load, the first pad part and the second pad part being opposed to each other in a planar direction of the surface of the semiconductor substrate to define an opposing region as a clearance therebetween; and

a surface protection film that has an electrical insulating property and is disposed at least in the opposing region, wherein

the surface protection film is a silicon nitride film or a silicon oxide film, and has a thickness of 1 μm or more, and

the surface protection film includes first portions covering at least portions of surfaces of the first and second pad parts opposite to the hard film, second portions extending from the first portions and along opposing side surfaces of the first and second pad parts, and a third portion connecting between the second portions and being in contact with a part of the hard film exposed in the opposing region.

2. The semiconductor device according to claim 1 , wherein

at least one of the pad parts has an exposed region that is exposed from the surface protection film, and

the exposed region is provided at a position that overlaps with a region where the semiconductor element is disposed in a projection view in a thickness direction of the semiconductor substrate.

3. The semiconductor device according to claim 1 , wherein:

the second pad part is electrically connected to the inductive load, and the semiconductor element is turned on and off to control a current flowing in the inductive load.

4. A semiconductor device comprising:

a semiconductor substrate that includes a semiconductor element disposed on a surface of the semiconductor substrate;

an interlayer dielectric film that is disposed on the surface of the semiconductor substrate;

a wiring layer that is disposed in the interlayer dielectric film;

a hard film that is disposed opposite to the semiconductor substrate with respect to the interlayer dielectric film and that is harder than the interlayer dielectric film;

a plurality of pad parts for external connection that are disposed opposite to the interlayer dielectric film with respect to the hard film and that are connected via the wiring layer to the semiconductor element, the plurality of pad parts including a first pad part and a second pad part being opposed to each other in a planar direction of the surface of the semiconductor substrate to define an opposing region as a clearance therebetween; and

a surface protection film that has an electrical insulating property and is disposed at least in the opposing region, wherein

the surface protection film includes an inner film and an outer film, the outer film being disposed opposite to the first and second pad parts with respect to the inner film,

the inner film has a thickness of 1 μm or more and is harder than the outer film, and

the inner film includes first portions covering at least portions of surfaces of the first and second pad parts opposite to the hard film, second portions extending from the first portions and along opposing side surfaces of the first and second pad parts, and a third portion connecting between the second portions and being in contact with a part of the hard film exposed in the opposing region.

5. The semiconductor device according to claim 4 , wherein

the inner film is a silicon nitride film or a silicon oxide film.

6. The semiconductor device according to claim 4 , wherein

at least one of the pad parts has an exposed region that is exposed from the surface protection film, and

the exposed region is provided at a position that overlaps with a region where the semiconductor element is disposed in a projection view in a thickness direction of the semiconductor substrate.

7. The semiconductor device according to claim 4 , wherein:

the second pad part is electrically connected to the inductive load, and the semiconductor element is turned on and off to control a current flowing in the inductive load.

8. The semiconductor device according to claim 4 , wherein

the surface protection film is disposed opposite to the hard film with respect to the first and second pad parts, and defines a top surface of the semiconductor device, and

the first and second pad parts are partly exposed from the surface protection film to define the top surface of the semiconductor device with the surface protection film and to define bonding regions for the external connection.

9. The semiconductor device according to claim 4 , wherein

each of the first pad part and the second pad part has a plurality of exposed regions exposed from the surface protection film,

the plurality of exposed regions is aligned in an alignment direction orthogonal to an opposing direction in which the first pad part and the second pad part are opposed to each other, and

the opposing region extends in the alignment direction.

10. The semiconductor device according to claim 9 , wherein

the surface protection film is disposed in an entirety of the opposing region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2019
From: ASHIDA, YOUICHI; FUJIWARA, TSUYOSHI
To: DENSO CORPORATION
Reel/Frame 048619/0503 →
Priority Claims (1)
JP 2016-202787 · Oct 14, 2016 · national
Continuity (2)
Continuation PCTJP2017030227 · Aug 24, 2017
Related Publication 20190214346A1 · Jul 11, 2019