Nanosheet devices with improved electrostatic integrity
Semiconductor devices and methods of forming the same include forming spacers on respective sidewalls above a stack of alternating channel layers and sacrificial layers, leaving an opening between the spacers. The stack is etched, between the spacers, to form a central opening in the stack that separates the channel layers into respective pairs of channel structures. The sacrificial material is etched away to expose top and bottom surfaces of the channel structures. A gate stack is formed on, between, and around the channel structures, including in the central opening between pairs of channel structures.
1. A method of forming a semiconductor device, comprising:
forming spacers on respective sidewalls above a stack of alternating channel layers and sacrificial layers, leaving an opening between the spacers;
etching down into the stack, between the spacers, to form a central opening in the stack that separates the channel layers into respective pairs of channel structures;
etching away the sacrificial layers to expose top and bottom surfaces of the channel structures; and
forming a gate stack on, between, and around the channel structures, including in the central opening between pairs of channel structures.
2. The method of claim 1 , further comprising depositing sacrificial material in the central opening in the stack, the sacrificial material connecting the sacrificial layers to form a sacrificial structure.
3. The method of claim 2 , further comprising:
forming a dummy gate over the stack;
forming spacers on sidewalls of the dummy gate; and
etching away the dummy gate, wherein etching away the sacrificial layers is performed after etching away the dummy gate and further includes etching away the sacrificial structure between vertically adjacent channel structures as well as between horizontally adjacent channel structures.
4. The method of claim 3 , further comprising forming inner spacers by recessing the sacrificial structure relative to the channel structures and depositing a dielectric material in the recesses.
5. The method of claim 4 , wherein the inner spacers have a vertical central portion and a plurality of horizontal portions that extend outward from sides of the central portion, between the channel structures.
6. The method of claim 3 , further comprising:
etching away the stack of alternating channel layers and sacrificial layers in regions that are not covered by the dummy gate after forming the dummy gate; and
growing source/drain structures from exposed sidewalls of the channel structures.
7. The method of claim 1 , wherein forming the spacers comprises:
depositing a directed self-assembly material in a recess above the stack to form an inner portion and outer portions;
etching away the inner portion to form an opening between the outer portions; and
etching down into a dielectric layer above the stack to form the spacers and the opening between the spacers.
8. The method of claim 1 , further comprising forming the stack of alternating channel layers and sacrificial layers on a base layer.
9. The method of claim 8 , further comprising etching away the base layer before etching away the sacrificial layers.
10. The method of claim 9 , further comprising depositing a bottom isolation layer under the stack of alternating channel layers after etching away the base layer and before etching away the sacrificial layers.
11. A method of forming a semiconductor device, comprising:
forming spacers on respective sidewalls above a stack of alternating channel layers and sacrificial layers, leaving an opening between the spacers;
etching down into the stack, between the spacers, to form a central opening in the stack that separates the channel layers into respective pairs of channel structures;
depositing sacrificial material in the central opening in the stack, the sacrificial material connecting the sacrificial layers to form a sacrificial structure;
forming a dummy gate over the stack;
etching away the stack of alternating channel layers in regions not covered by the dummy gate;
forming inner spacers by recessing the sacrificial structure relative to the channel structures and depositing a dielectric material in the recesses;
growing source and drain regions from sidewalls of the channel structures;
etching away the sacrificial structure to expose top and bottom surfaces of the channel structures; and
forming a gate stack on, between, and around the channel structures, including in the central opening between pairs of channel structures.
12. The method of claim 11 , further comprising:
forming spacers on sidewalls of the dummy gate; and
etching away the dummy gate, wherein etching away the sacrificial structure is performed after etching away the dummy gate and further includes etching away the sacrificial structure between vertically adjacent channel structures as well as between horizontally adjacent channel structures.
13. The method of claim 12 , wherein the inner spacers have a vertical central portion and a plurality of horizontal portions that extend outward from sides of the central portion, between the channel structures.
14. The method of claim 11 , wherein forming the spacers comprises:
depositing a directed self-assembly material in a recess above the stack to form an inner portion and outer portions;
etching away the inner portion to form an opening between the outer portions; and
etching down into a dielectric layer above the stack to form the spacers and the opening between the spacers.
15. The method of claim 11 , further comprising etching away the base layer before etching away the sacrificial structure.
16. The method of claim 11 , further comprising depositing a bottom isolation layer under the stack of alternating channel layers after etching away the base layer and before etching away the sacrificial structure.