IP Library › Granted Patent US 10,917,251
Granted Patent B2
US 10,917,251 · App. 15/942,181 · Granted Feb 9, 2021

Apparatus and method for generating hybrid static/dynamic entropy physically unclonable function

Inventors: Sudhir Satpathy (Hillsboro, OR); Vikram Suresh (Portland, OR); Sanu Mathew (Portland, OR)
Assignee: Intel Corporation
H04L9/3278H04L9/006G06F7/588
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Quick Facts
Patent No.
US 10,917,251
App. No.
15/942,181
Granted
Feb 9, 2021
Kind
B2
Abstract

An apparatus is provided which comprises: an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells; a first circuitry coupled to the entropy source, wherein the first circuitry to generate an entropy source selection set; and a second circuitry coupled to the entropy source and the first circuitry, wherein the second circuitry is to receive the first random sequence and the entropy source selection set, and wherein the second circuitry is to generate a second random sequence.

Claims (38)

1. An apparatus comprising:

an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells;

a first circuitry coupled to the entropy source, wherein the first circuitry is to receive the first random sequence and to generate a bias quantification information; and

a second circuitry coupled to the first circuitry, wherein the second circuitry is to receive the bias quantification information and to generate an entropy source selection (ESS) set, wherein the second circuitry comprises an Entropy Source Selection circuitry, to generate a Bias Map based on the bias quantification information.

2. The apparatus of claim 1 , wherein the entropy source comprises a Physically Unclonable Function (PUF) array, and wherein the bi-stable cross-coupled inverter cells comprise identically laid-out matched devices.

3. The apparatus of claim 1 , wherein the first circuitry comprises a Temporal Majority Voting (TMV) circuitry, and wherein the TMV circuitry is to accumulate an output of each bi-stable cross-coupled inverter cell for some consecutive cycles to generate the bias quantification information.

4. The apparatus of claim 3 , wherein the TMV circuitry comprises an up/down counter that is to progressively count up and to switch into down counting mode on reaching saturation value, and wherein the TMV circuitry comprises of a bias quantification circuitry to enable quick selection of unbiased or least biased cells for TRNG operation.

5. The apparatus of claim 3 , wherein the TMV circuitry comprises a bias quantification circuitry to enable quick selection of unbiased or least biased cells for TRNG operation.

6. The apparatus of claim 1 , wherein the bias quantification information is to identify the bi-stable cross-coupled inverter cells in the array of the entropy source that are unstable.

7. The apparatus of claim 1 , wherein the Entropy Source Selection circuitry is to generate the entropy source selection set based on the Bias Map.

8. The apparatus of claim 1 , wherein the entropy source selection set comprises N most unstable bi-stable cross-coupled inverter cells in the array, wherein N is an integer number.

9. An apparatus to generate random bits, the apparatus comprising:

an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells;

a first circuitry coupled to the entropy source, wherein the first circuitry is to generate an entropy source selection set; and

a second circuitry coupled to the entropy source and the first circuitry, wherein the second circuitry is to receive the first random sequence and the entropy source selection set, and wherein the second circuitry to generate a second random sequence, wherein the second circuitry comprises a Hierarchical Von Neumann (HVN) extractor circuitry, and wherein the Hierarchical Von Neumann (HVN) extractor circuitry comprises of at least two Von Neumann (VN) extractor circuits.

10. The apparatus of claim 9 , wherein the entropy source comprises a Physically Unclonable Function (PUF) array, and wherein the bi-stable cross-coupled inverter cells comprise of identically laid-out matched devices.

11. The apparatus of claim 9 , wherein the entropy source selection set comprises N most unstable bi-stable cross-coupled inverter cells in the array of the entropy source, wherein N is an integer number.

12. A system comprising:

a memory;

a processor coupled to the memory; and

a wireless interface to allow the processor to communicate with another device, wherein the processor comprises:

an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells;

a first circuitry coupled to the entropy source, wherein the first circuitry is to receive the first random sequence and to generate a bias quantification information; and

a second circuitry coupled to the first circuitry, wherein the second circuitry is to receive the bias quantification information and to generate an entropy source selection set, wherein the second circuitry comprises an Entropy Source Selection circuitry, to generate a Bias Map based on the bias quantification information.

13. The system of claim 12 , wherein the entropy source comprises a Physically Unclonable Function (PUF) array, and wherein the bi-stable cross-coupled inverter cells comprise identically laid-out matched devices.

14. The system of claim 12 , wherein the first circuitry comprises a Temporal Majority Voting (TMV) circuitry, and wherein the TMV circuitry is to accumulate an output of each bi-stable cross-coupled inverter cell for some consecutive cycles to generate the bias quantification information.

15. The system of claim 14 , wherein the TMV circuitry comprises an up/down counter that is to progressively count up and to switch into down counting mode on reaching saturation value, and wherein the TMV circuitry comprises of a bias quantification circuitry to enable quick selection of unbiased or least biased cells for TRNG operation.

16. The system of claim 14 , wherein the TMV circuitry comprises a bias quantification circuitry to enable quick selection of unbiased or least biased cells for TRNG operation.

17. The system of claim 12 , wherein the bias quantification information is to identify the bi-stable cross-coupled inverter cells in the array of the entropy source that are unstable.

18. The system of claim 12 , wherein the Entropy Source Selection circuitry is to generate the entropy source selection set based on the Bias Map.

19. The system of claim 12 , wherein the entropy source selection set comprises N most unstable bi-stable cross-coupled inverter cells in the array, wherein N is an integer number.

20. An apparatus comprising:

an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells;

a first circuitry coupled to the entropy source, wherein the first circuitry is to receive the first random sequence and to generate a bias quantification information, wherein the first circuitry comprises a Temporal Majority Voting (TMV) circuitry, wherein the TMV circuitry comprises an up/down counter that is to progressively count up and to switch into down counting mode on reaching saturation value; and

a second circuitry coupled to the first circuitry, wherein the second circuitry is to receive the bias quantification information and to generate an entropy source selection (ESS) set.

21. The apparatus of claim 20 , wherein the TMV circuitry is to accumulate an output of each bi-stable cross-coupled inverter cell for some consecutive cycles to generate the bias quantification information.

22. The apparatus of claim 20 , wherein the TMV circuitry comprises a bias quantification circuitry to enable quick selection of unbiased or least biased cells for TRNG operation.

23. The apparatus of claim 20 , wherein the second circuitry comprises an Entropy Source Selection circuitry, to generate a Bias Map based on the bias quantification information.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2018
From: SATPATHY, SUDHIR; SURESH, VIKRAM; MATHEW, SANU
To: INTEL CORPORATION
Reel/Frame 045492/0045 →
Continuity (1)
Related Publication 20190305970A1 · Oct 3, 2019
Cited By (1)
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