System and method to improve nested virtual machine monitor performance

1. A processing system, comprising:

a first register to store an invalidation mode flag associated with a virtual processor identifier (VPID); and

a processing core, communicatively coupled to the first register, the processing core comprising a logic circuit to execute a virtual machine monitor (VMM) environment, the VMM environment comprising a root mode VMM supporting a non-root mode VMM, the non-root mode VMM to execute a virtual machine (VM) identified by the VPID, the logic circuit further comprising an invalidation circuit to:

execute a virtual processor invalidation (INVVPID) instruction issued by the non-root mode VMM, the INVVPID instruction comprising a reference to an INVVPID descriptor that specifies a linear address and the VPID; and

responsive to determining that the invalidation mode flag is set, invalidate, without triggering a VM exit event, a memory address mapping associated with the linear address.

2. The processing system of claim 1 , wherein the memory address mapping is one of a linear mapping or a combined mapping,

wherein the linear mapping translates the linear address associated with a guest application executed by the virtual machine (VM) to a host physical address (HPA) associated with a memory, and

wherein the combined mapping comprises a first translation from the linear address to a guest physical address (GPA) associated with the VM and a second translation from the GPA to the HPA.

3. The processing system of claim 2 , further comprising a memory management unit (MMU), wherein the MMU is to translate, using an extended page table (EPT), the GPA to the HPA, and wherein the EPT comprises the VPID and the second translation from the GPA to the HPA of the combined mapping.

4. The processing system of claim 1 wherein the processing core further comprises:

a translation lookaside buffer (TLB) to, responsive to performing the memory address mapping, store a cached copy the memory address mapping.

5. The processing system of claim 4 , wherein responsive to determining that the invalidation mode flag is not set, the invalidation circuit is to:

trigger the VM exit event; and

flush all TLB entries except for the TLB entries associated with the root mode VMM.

6. The processing system of claim 1 , further comprising:

a second register to store an invalidation type, wherein the invalidation type is one of an individual-address invalidation, a single-context invalidation, all-context invalidation, or a single-context-retaining-global invalidation, wherein responsive to determining that the invalidation mode flag is set, the invalidation circuit is further to:

determine that the invalidation type is the individual-address invalidation;

invalidate the memory address mapping associated with the linear address; and

flush the TLB entry corresponding to the invalidated memory address mapping.

7. The processing system of claim 6 , wherein responsive to determining that the invalidation mode flag is set, the invalidation circuit is further to:

determine that the invalidation type is the single-context invalidation;

invalidate all memory address mappings associated with the VPID; and

flush all the TLB entries corresponding to the invalidated memory address mappings.

8. The processing system of claim 6 , wherein responsive to determining that the invalidation mode flag is set, the invalidation circuit is further to:

determine that the invalidation type is the all-context invalidation;

invalidate all memory address mappings except for memory address mappings associated with the root mode VMM; and

flush all TLB entries corresponding to the invalidated memory address mappings.

9. The processing system of claim 6 , wherein responsive to determining that the invalidation mode flag is set, the logic circuit is further to:

determine that the invalidation type is the single-context-retaining-global invalidation; and

invalidate all memory address mappings except for memory address mappings identified as global memory translation.

10. A system comprising:

a memory; and

a processor, communicatively coupled to the memory, comprising:

a first register to store an invalidation mode flag associated with a virtual processor identifier (VPID); and

a processing core, communicatively coupled to the first register, the processing core comprising a logic circuit to execute a virtual machine monitor (VMM) environment, the VMM environment comprising a root mode VMM supporting a non-root mode VMM, the non-root mode VMM to execute a virtual machine (VM) identified by the VPID, the logic circuit further comprising an invalidation circuit to:

execute a virtual processor invalidation (INVVPID) instruction issued by the non-root mode VMM, the INVVPID instruction comprising a reference to an INVVPID descriptor that specifies a linear address and the VPID; and

responsive to determining that the invalidation mode flag is set, invalidate, without triggering a VM exit event, a memory address mapping associated with the linear address.

11. The system of claim 10 , wherein the memory address mapping is one of a linear mapping or a combined mapping,

wherein the linear mapping translates the linear address associated with a guest application executed by the virtual machine (VM) to a host physical address (HPA) associated with a memory, and

wherein the combined mapping comprises a first translation from the linear address to a guest physical address (GPA) associated with the VM and a second translation from the GPA to the HPA.

12. The system of claim 11 , wherein the processing core further comprises:

a translation lookaside buffer (TLB) to, responsive to performing the memory address translation, store a cached copy the memory address mapping.

13. The system of claim 12 , wherein responsive to determining that the invalidation mode flag is not set, the invalidation circuit is to:

trigger the VM exit event; and

flush all TLB entries except for the TLB entries associated with the root mode VMM.

14. The system of claim 10 , further comprising:

a second register to store an invalidation type, wherein the invalidation type is one of an individual-address invalidation, a single-context invalidation, all-context invalidation, or a single-context-retaining-global invalidation, wherein responsive to determining that the invalidation mode flag is set, the invalidation circuit is further to:

determine that the invalidation type is the individual-address invalidation;

invalidate the memory address mapping associated with the linear address; and

flush the TLB entry corresponding to the invalidated memory address mapping.

15. The system of claim 14 , wherein responsive to determining that the invalidation mode flag is set, the invalidation circuit is further to:

determine that the invalidation type is the single-context invalidation;

invalidate all memory address mappings associated with the VPID; and

flush all the TLB entries corresponding to the invalidated memory address mappings.

16. The system of claim 14 , wherein responsive to determining that the invalidation mode flag is set, the invalidation circuit is further to:

determine that the invalidation type is the all-context invalidation;

invalidate all memory address mappings except for memory address mappings associated with the root mode VMM; and

flush all TLB entries corresponding to the invalidated memory address mappings.

17. The system of claim 14 , wherein responsive to determining that the invalidation mode flag is set, the invalidation circuit is further to:

determine that the invalidation type is the single-context-retaining-global invalidation; and

invalidate all memory address mappings except for memory address mappings identified as global memory translation.

18. A method comprising:

executing, by a processing device, a virtual machine monitor (VMM) environment, the VMM environment comprising a root mode VMM supporting a non-root mode VMM, the non-root mode VMM executing a first virtual machine (VM) identified by a first virtual processor identifier (VPID), wherein the processing device comprises a first register to store an invalidation mode flag associated with the first VPID;

executing a virtual processor invalidation (INVVPID) instruction issued by a non-root mode VMM, the INVVPID instruction comprising a reference to an INVVPID descriptor that specifies a linear address and the first VPID; and

responsive to determining that the invalidation mode flag is set, invalidating, without triggering a VM exit event, a memory address mapping associated with the linear address.

19. The method of claim 18 , wherein the memory address mapping is one of a linear mapping or a combined mapping,

wherein the linear mapping translates the linear address associated with a guest application executed by the virtual machine (VM) to a host physical address (HPA) associated with a memory, and

wherein the combined mapping comprises a first translation from the linear address to a guest physical address (GPA) associated with the VM and a second translation from the GPA to the HPA.

20. The method of claim 19 , wherein the processing device further comprises:

a second register to store an invalidation type, wherein the invalidation type is one of an individual-address invalidation, a single-context invalidation, all-context-invalidation, or a single-context-retaining-global invalidation; and

a translation lookaside buffer (TLB) to, responsive to performing the memory address translation, store a cached copy the memory address mapping.

21. The method of claim 20 , further comprising:

responsive to determining the invalidation type is the individual-address invalidation,

invalidating the memory address mapping associated with the linear address; and

flushing the TLB entry corresponding to the invalidated memory address mapping;

responsive to determining that the invalidation type is the single-context invalidation,

invalidating all memory address mappings associated with the VPID; and

flushing all the TLB entries corresponding to the invalidated memory address mappings;

responsive to determining that the invalidation type is the all-context invalidation,

invalidating all memory address mappings except for memory address mappings associated with the root mode VMM; and

flushing all the TLB entries corresponding to the invalidated memory address mappings; and

responsive to determining that the invalidation type is the single-context-retaining-global invalidation, invalidating all memory address mappings except for memory address mappings identified as global memory translation.

22. The method of claim 20 , further comprising:

detecting that the non-root mode VMM assigns a second VPID to a second VM;

determining that the second VPID is a duplicate of a third VPID associated with a guest application previously generated by the root mode VMM;

executing a second INVVPID instruction to invalidate all memory address mappings associated with the third VPID; and

assigning a fourth VPID to the guest application, wherein the fourth VPID is different from the second VPID.