Gate driver and electroluminescent display including the same
A gate driver can include a plurality of stages, each of the plurality of stages including a transistor T 1 configured to apply a start signal of a gate-on voltage to a node Q in response to a clock signal and activate the node Q; a transistor T 7 configured to supply an emission signal of the gate-on voltage to an output node when a node QA is bootstrapped in synchronization with a timing at which the node Q is activated; a QB controller configured to activate a node QB based on the clock signal, the start signal and a voltage of the node Q; and a transistor T 8 configured to supply the emission signal of a gate-off voltage to the output node while the node QB is activated prior to activation of the node Q.
1. A gate driver comprising:
a plurality of stages, each of the plurality of stages including:
a first transistor configured to apply a start signal of a gate-on voltage to a first node in response to a first clock signal and activate the first node;
a second transistor configured to supply an emission signal of the gate-on voltage to an output node when a second node is bootstrapped in response to a second clock signal, wherein the second clock signal has a phase different from a phase of the first clock signal;
a first controller configured to activate a third node based on the first clock signal, the start signal and a voltage of the first node; and
a third transistor configured to supply the emission signal of a gate-off voltage to the output node while the third node is activated prior to activation of the first node,
wherein each of the plurality of stages further includes a fifth transistor configured to block an electrical connection between the first node and the second node when the second node is bootstrapped.
2. The gate driver of claim 1 , wherein each of the plurality of stages further includes:
a first capacitor connected between the second node and a fourth node; and
a fourth transistor configured to switch in accordance with the first node and supply the second clock signal to the fourth node,
wherein the first capacitor is configured to reflect a change in a voltage of the second clock signal to a voltage of the second node and bootstrap the second node, in response to the second clock signal changing from the gate-off voltage to the gate-on voltage.
3. The gate driver of claim 2 , wherein a voltage of the fourth node is the gate-off voltage while a voltage of the first node is held at the gate-off voltage, and
wherein a voltage of the fourth node is synchronized with the second clock signal while the voltage of the first node is held at a voltage less than or equal to the gate-on voltage.
4. The gate driver of claim 2 , wherein when the second node is bootstrapped, a voltage of the first node is different from the voltage of the second node.
5. The gate driver of claim 1 , wherein a gate electrode of the fifth transistor is connected to an input terminal of the gate-on voltage, a first electrode of the fifth transistor is connected to the first node, and a second electrode of the fifth transistor is connected to the second node.
6. The gate driver of claim 1 , wherein the first controller includes:
a second capacitor connected between an input terminal of the first clock signal and a fifth node;
a sixth transistor configured to supply the first clock signal to the third node based on a voltage of the fifth node;
a seventh transistor configured to supply the gate-off voltage to the fifth node in response to the start signal; and
an eight configured to supply the gate-off voltage to the third node based on the voltage of the first node.
7. The gate driver of claim 6 , wherein the voltage of the fifth node changes in synchronization with the first clock signal while the start signal is held at the gate-off voltage, and
wherein the voltage of the fifth node is the gate-off voltage while the start signal is held at the gate-on voltage.
8. The gate driver of claim 1 , wherein the third transistor includes a ninth transistor and a tenth transistor, wherein the ninth transistor is connected in series with the tenth transistor,
wherein a gate electrode of the ninth transistor is connected to the third node, a first electrode of the ninth transistor is connected to the output node, and a second electrode of the ninth transistor is connected to a sixth node between the ninth transistor and tenth transistor, and
wherein a gate electrode of the tenth transistor is connected to the third node, a first electrode of the tenth transistor is connected to the sixth node, and a second electrode of the tenth transistor is connected to an input terminal of the gate-off voltage.
9. The gate driver of claim 8 , wherein each of the plurality of stages further includes an eleventh transistor configured to suppress a leakage current of the third transistor, and
wherein a gate electrode of the eleventh transistor is connected to the output node, a first electrode of the eleventh transistor is connected to an input terminal of the gate-on voltage, and a second electrode of the eleventh transistor is connected to the sixth node.
10. The gate driver of claim 1 , wherein the plurality of stages include odd-numbered stages and even-numbered stages, and each of the odd-numbered stages and the even-numbered stages include a first input terminal and a second input terminal,
wherein in each of the odd-numbered stages, the first clock signal is input to the first input terminal, and the second clock signal is input to the second input terminal, and
wherein in each of the even-numbered stages, the first clock signal is input to the second input terminal, and the second clock signal is input to the first input terminal.