Semiconductor structure having gate-all-around devices
View Patent ↗An integrated circuit includes gate-all-around (GAA) nanowire transistors and GAA nanosheet transistors on the same substrate. An array of cells including GAA nanowire transistors and cells including nanosheet transistors are provided. The cells including GAA nanowire transistors can be adjacent cells including GAA nanosheet transistors with isolation structures interposing the cells.
1. An integrated circuit, comprising:
a substrate;
a first cell comprising a first gate-all-around (GAA) nanowire transistor on the substrate, the first GAA nanowire transistor has vertically stacked multiple nanowire channels, a first gate dielectric layer wrapping around the nanowire channels, and a first gate electrode wrapping around the first gate dielectric layer;
a second cell comprising a second GAA nanosheet transistor on the substrate, the second GAA nanosheet transistor having vertically stacked multiple nanosheet channels, a second gate dielectric layer wrapping around the nanosheet channels, and a second gate electrode wrapping around the second gate dielectric layer; and
an isolation structure interposing the first cell and the second cell, wherein the isolation structure includes at least one of a dielectric gate or a metal gate.
2. The integrated circuit of claim 1 , wherein the isolation structure is the dielectric gate.
3. The integrated circuit of claim 1 , wherein the isolation structure is the metal gate.
4. The integrated circuit of claim 1 , wherein the first cell and the second cell each have a first height in a first direction.
5. The integrated circuit of claim 4 , wherein the first cell has a first width in a second direction and the second cell has a second width in the second direction, wherein the second width is greater than the first width.
6. The integrated circuit of claim 1 , wherein nanowire channels have a first width and the nanosheet channels have a second width, wherein a ratio of the second width to the first width is in a range of 1.3 to 10.
7. The integrated circuit of claim 1 , wherein the isolation structure includes two dielectric gates.
8. The integrated circuit of claim 7 , wherein the two dielectric gates extend into the substrate.
9. The integrated circuit of claim 1 , wherein the isolation structure includes a dummy channel region.
10. An integrated circuit, comprising:
an array of cells formed on a substrate;
wherein a first row of the array of cells includes a first cell comprising a first gate-all-around (GAA) nanowire transistor and a second cell comprising a second GAA nanosheet transistor, wherein the second cell is a next adjacent cell in the first row to the first cell;
a second row of the array of cells, wherein the second row consists of cells with nanowire transistors; and
an isolation structure interposing the first cell and the second cell.
11. The integrated circuit of claim 10 , wherein the isolation structure includes a non-functional gate.
12. The integrated circuit of claim 10 , wherein the first GAA nanowire transistor has a first channel width and the second GAA nanosheet transistor has a second channel width, a ratio of the second channel width to the first channel width being between approximately 1.3 and 10.
13. The integrated circuit of claim 10 , wherein the first GAA nanowire transistor and the second GAA nanosheet transistor have a same gate length.
14. The integrated circuit of claim 10 , wherein the first GAA nanowire transistor and the second GAA nanosheet transistor have a same gate dielectric thickness.
15. The integrated circuit of claim 10 , further comprising: a gate end dielectric structure formed on a face of a gate end of the first GAA nanowire transistor, the gate end dielectric structure providing an isolation to a cell of a second row of the array of cells.
16. The integrated circuit of claim 10 , wherein the isolation structure includes a dielectric gate or a metal gate.
17. An integrated circuit, comprising:
a first row of an array of cells disposed on a substrate, wherein the first row includes:
first cell comprising a first gate-all-around (GAA) nanowire transistor on the substrate, the first GAA nanowire transistor has vertically stacked multiple nanowire channels, a first gate dielectric layer wrapping around the nanowire channels, and a first gate electrode wrapping around the first gate dielectric layer; and
a second cell comprising a second GAA nanosheet transistor on the substrate, the second GAA nanosheet transistor having vertically stacked multiple nanosheet channels, a second gate dielectric layer wrapping around the nanosheet channels, and a second gate electrode wrapping around the second gate dielectric layer; and
an isolation structure interposing the first cell and the second cell; and
a second row of the array of cells, wherein the second row includes a third cell and a fourth cell, wherein the third cell includes a third GAA nanowire transistor and the fourth cell includes a fourth GAA nanowire transistor.
18. The integrated circuit of claim 17 , wherein the third cell is a next adjacent cell to the fourth cell.
19. The integrated circuit of claim 17 , wherein the nanosheet channels and nanowire channels extend to interface the isolation structure.
20. The integrated circuit of claim 19 , wherein the isolation structure is a dielectric gate.