Electroluminescence display device

1. An electroluminescence display device, comprising:

a first active layer including a poly silicon channel;

a first gate insulating layer covering the first active layer;

a first gate line arranged on the first gate insulating layer to intersect the first active layer;

a first interlayer insulating film covering the first gate line and the first active layer;

a second active layer disposed on the first interlayer insulating film and forming an oxide channel different from the poly silicon channel of the first active layer;

a second gate insulating layer on the second active layer; and

a second gate line arranged on the second gate insulating layer to intersect the second active layer, the first gate line and the second gate line being overlapped with each other, and the first gate line and the second gate line supplying a same gate signal,

wherein the first active layer and the second active layer are not overlapped with each other,

wherein the first gate line and the second gate line are parallel and each have a widest width in a first area where the first gate line and the second gate line overlap the second active layer in a plan view, and

wherein the widest widths of the first gate line and the second gate line in the first area where the first gate line and the second gate line overlap the second active layer are greater than each width of the first gate line and the second gate line in a second area where the first gate line and the second gate line overlap the first active layer in the plan view.

2. The electroluminescence display device of claim 1 , further comprising:

a second interlayer insulating film covering the second active layer and the second gate line; and

a source/drain layer arranged on the second active layer,

wherein the source/drain layer is connected with the second active layer through first and second contact holes formed in the second interlayer insulating film.

3. The electroluminescence display device of claim 2 , wherein the source/drain layer is additionally arranged on the first active layer, and is connected with the first active layer through a third contact hole formed in the first gate insulating layer, the first interlayer insulating film and the second interlayer insulating film of the electroluminescence display device.

4. The electroluminescence display device of claim 1 , wherein the first gate line and the second gate line are connected with a respective gate electrode of a first switching transistor and a second switching transistor provided in pixels provided in a display area of the electroluminescence display device, and the gate electrodes of the first switching transistor and the second switching transistor are connected with the first active layer and the second active layer of each of the pixels.

5. The electroluminescence display device of claim 1 , wherein the first gate line and the second gate line are connected with each other through a first gate contact hole and a second gate contact hole arranged on first and second gate in panel (GIP) circuit portions each located at opposite sides of a display area of the electroluminescence display device.

6. The electroluminescence display device of claim 1 , wherein the polysilicon channel is a low temperature polysilicon (LTPS) channel.

7. An electroluminescence display device, comprising:

a first active layer including a poly silicon channel;

a first gate insulating layer covering the first active layer;

a first gate line arranged on the first gate insulating layer to intersect the first active layer;

a first interlayer insulating film covering the first gate line and the first active layer;

a second active layer disposed on the first interlayer insulating film and forming an oxide channel different from the poly silicon channel of the first active layer;

a second gate insulating layer on the second active layer; and

a second gate line arranged on the second gate insulating layer to intersect the second active layer, the second gate line being superimposed on the first gate line, and being separated from the first gate line by the first gate insulating layer and the second gate insulating layer,

wherein the first active layer and the second active layer are not overlapped with each other,

wherein the first gate line and the second gate line are parallel and each have a widest width in a first area where the first gate line and the second gate line overlap the second active layer in a plan view, and

wherein the widest widths of the first gate line and the second gate line in the first area where the first gate line and the second gate line overlap the second active layer are greater than each width of the first gate line and the second gate line in a second area where the first gate line and the second gate line overlap the first active layer in the plan view.

8. The electroluminescence display device of claim 7 , wherein an area of the first gate line is greater than an area of the second gate line.

9. The electroluminescence display device of claim 7 , wherein the first gate line and the second gate line supply a same gate signal.

10. The electroluminescence display device of claim 7 , further comprising a source/drain layer arranged on the second active layer,

wherein a second interlayer insulating film covers the second active layer and the second gate line, and

wherein the source/drain layer is connected with the second active layer through first and second contact holes formed in the second interlayer insulating film.

11. The electroluminescence display device of claim 10 , wherein the source/drain layer is additionally arranged on the first active layer, and is connected with the first active layer through a third contact hole formed in the first gate insulating layer, the first interlayer insulating film and the second interlayer insulating film of the electroluminescence display device.

12. The electroluminescence display device of claim 7 , wherein the first gate line and the second gate line are connected with a respective gate electrode of a first switching transistor and a second switching transistor provided in pixels provided in a display area of the electroluminescence display device, and the gate electrodes of the first switching transistor and the second switching transistor are connected with the first active layer and the second active layer of each of the pixels.

13. The electroluminescence display device of claim 7 , wherein the first gate line and the second gate line are connected with each other through a first gate contact hole and a second gate contact hole arranged on first and second gate in panel (GIP) circuit portions each located at opposite sides of a display area of the electroluminescence display device.

14. An electroluminescence display device, comprising:

a first active layer including a poly silicon channel;

a first gate insulating layer covering the first active layer;

a first gate line arranged on the first gate insulating layer to intersect the first active layer;

a first interlayer insulating film covering the first gate line and the first active layer;

a second active layer disposed on the first interlayer insulating film and forming an oxide channel different from the poly silicon channel of the first active layer;

a second gate insulating layer on the second active layer; and

a second gate line arranged on the second gate insulating layer to intersect the second active layer, the first gate line and the second gate line supplying a same gate signal,

wherein the first active layer and the second active layer are not overlapped with each other,

wherein the first gate line and the second gate line are parallel and each have a widest width in a first area where the first gate line and the second gate line overlap the second active layer in a plan view, and

wherein the widest widths of the first gate line and the second gate line in the first area where the first gate line and the second gate line overlap the second active layer are greater than each width of the first gate line and the second gate line in a second area where the first gate line and the second gate line overlap the first active layer in the plan view.