Substrate for a temperature-compensated surface acoustic wave device or volume acoustic wave device

1. A surface acoustic wave device, comprising:

a piezoelectric layer;

a stiffening substrate, wherein a ratio of a thickness of the piezoelectric layer to a thickness of the stiffening substrate is less than or equal to 0.125;

a semiconductor layer disposed between the piezoelectric layer and the stiffening substrate; at least two interdigitated metallic comb electrodes on a surface of the piezoelectric layer for generating or receiving surface acoustic waves at the surface of the piezoelectric layer;

a first dielectric layer between the piezoelectric layer and the semiconductor layer; and

a charge-trapping layer at an interface between the first dielectric layer and the semiconductor layer and/or an interface between the first dielectric layer and the piezoelectric layer.

2. The surface acoustic wave device of claim 1 , wherein the piezoelectric layer is monocrystalline.

3. The surface acoustic wave device of claim 1 , wherein the piezoelectric layer comprises a material selected from the group consisting of: lithium niobate (LiNbO3), lithium tantalate (LiTaO3), and quartz.

4. The surface acoustic wave device of claim 1 , wherein the thickness of the piezoelectric layer is less than 50 μm, and the thickness of the stiffening substrate is between 400 and 800 μm.

5. The surface acoustic wave device of claim 4 , wherein the thickness of the piezoelectric layer is less than 20 μm.

6. The surface acoustic wave device of claim 5 , wherein the thickness of the piezoelectric layer is less than 1 μm.

7. The surface acoustic wave device of claim 1 , wherein a thickness of the semiconductor layer is between 10 nm and 2 μm.

8. The surface acoustic wave device of claim 1 , wherein the semiconductor layer comprises a material selected from the group consisting of: silicon, germanium, SiGe, SiC, and a III-V material.

9. The surface acoustic wave device of claim 1 , wherein the semiconductor layer comprises at least one electronic component.

10. The surface acoustic wave device of claim 9 , wherein the at least one electronic component comprises a component selected from the group consisting of: a CMOS transistor, a switch, and a power amplifier.

11. The surface acoustic wave device of claim 1 , wherein the charge-trapping layer comprises polycrystalline silicon.

12. The surface acoustic wave device of claim 1 , wherein the first dielectric layer comprises silicon oxide.

13. The surface acoustic wave device of claim 1 , wherein the stiffening substrate comprises sapphire, glass and/or spinel (MgAl2O4).

14. A surface acoustic wave device, comprising:

a stiffening substrate;

a piezoelectric layer;

a semiconductor layer disposed between the piezoelectric layer and the stiffening substrate;

a first dielectric layer between the piezoelectric layer and the semiconductor layer;

a charge-trapping layer between the first dielectric layer and the semiconductor layer and/or between the first dielectric layer and the piezoelectric layer; and

at least two interdigitated metallic comb electrodes on a surface of the piezoelectric layer for generating or receiving surface acoustic waves at the surface of the piezoelectric layer, wherein the at least two interdigitated metallic comb electrodes are covered with a second dielectric layer.

15. The surface acoustic wave device of claim 14 , wherein the piezoelectric layer is monocrystalline.

16. The surface acoustic wave device of claim 14 , wherein a ratio of a thickness of the piezoelectric layer to a thickness of the stiffening substrate is less than or equal to 0.125.

17. The surface acoustic wave device of claim 16 , wherein the thickness of the piezoelectric layer is less than 50 μm, and the thickness of the stiffening substrate is between 400 and 800 μm.

18. The surface acoustic wave device of claim 17 , wherein the thickness of the piezoelectric layer is less than 20 μm.

19. The surface acoustic wave device of claim 18 , wherein the thickness of the piezoelectric layer is less than 1 μm.

20. The surface acoustic wave device of claim 14 , wherein a thickness of the semiconductor layer is between 10 nm and 2 μm.

21. The surface acoustic wave device of claim 14 , wherein the charge-trapping layer comprises polycrystalline silicon.

22. The surface acoustic wave device of claim 14 , wherein the first dielectric layer comprises silicon oxide.

23. The surface acoustic wave device of claim 14 , wherein the stiffening substrate comprises sapphire, glass and/or spinel (MgAl2O4).

24. A method of manufacturing a surface acoustic wave device, comprising:

transferring a semiconductor layer from a first donor substrate onto a stiffening substrate to form a support substrate;

forming a first dielectric layer over the semiconductor layer;

transferring a piezoelectric layer onto the support substrate from a second donor substrate such that material of the first dielectric layer and the semiconductor layer are disposed between the piezoelectric layer and the stiffening substrate, wherein the stiffening substrate has a coefficient of thermal expansion closer to a coefficient of thermal expansion of a material of the piezoelectric layer than that of silicon;

forming two interdigitated metallic comb electrodes on a surface of the piezoelectric layer; and

forming a charge-trapping layer at an interface between the first dielectric layer and the semiconductor layer and/or an interface between the first dielectric layer and the piezoelectric layer.

25. The method of claim 24 , wherein at least one transfer step comprises sub-steps as follows:

forming an embrittlement zone in the first or second donor substrate, respectively, by implantation of atomic species;

bonding the first or second donor substrate, respectively, onto the stiffening substrate or semiconductor layer, respectively; and

detaching the first or second donor substrate, respectively, along the embrittlement zone.

26. The method of claim 24 , wherein the first dielectric layer comprises silicon oxide.

27. The method of claim 24 , wherein the charge-trapping layer comprises a layer of polycrystalline silicon.

28. The method of claim 24 , further comprising covering the two interdigitated metallic comb electrodes with a second dielectric layer.

29. The method of claim 24 , wherein a thickness of the piezoelectric layer is less than 50 μm.

30. The method of claim 24 , wherein the semiconductor layer has a thickness between 10 nm and 2 μm.