Apparatus and method for channel coding in communication system

1. A device in a wireless communication network, comprising:

a processor, a memory and a transceiver;

wherein the processor, by executing program instructions stored in the memory, is configured to:

obtain an input sequence, wherein the input sequence comprises K bits of information, and K is a positive integer;

determine a lifting factor Z according to K;

encode the input sequence using an encoding matrix H, to obtain an encoded sequence; and

output the encoded sequence for transmission by the transceiver;

wherein the encoding matrix H is obtained from a low density parity check (LDPC) base graph by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns;

wherein the LDPC base graph comprises m rows and n columns, 5≤m≤46, and 27≤n≤68, and each element in the LDPC base graph has a value of 0 or 1;

wherein an element in the LDPC base graph has a value of 1 when:

i=0, j=0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, or 23;

i=1, j=0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, or 24;

i=2, j=0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, or 25;

i=3, j=0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, or 25;

i=4, j=0, 1, or 26;

wherein i is a row index of the LDPC base graph, 0≤i≤m, j is a column index of the LDPC base graph, 0≤j<n.

2. The device according to claim 1 , wherein the LDPC base graph comprises 46 rows and 68 columns, and wherein an element in the LDPC base graph has the value of 1 when:

i=0, j=0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, or 23;

i=1, j=0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, or 24;

i=2, j=0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, or 25;

i=3, j=0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, or 25;

i=4, j=0, 1, or 26;

i=5, j=0, 1, 3, 12, 16, 21, 22, or 27;

i=6, j=0, 6, 10, 11, 13, 17, 18, 20, or 28;

i=7, j=0, 1, 4, 7, 8, 14, or 29;

i=8, j=0, 1, 3, 12, 16, 19, 21, 22, 24, or 30;

i=9, j=0, 1, 10, 11, 13, 17, 18, 20, or 31;

i=10, j=1, 2, 4, 7, 8, 14, or 32;

i=11, j=0, 1, 12, 16, 21, 22, 23, or 33;

i=12, j=0, 1, 10, 11, 13, 18, or 34;

i=13, j=0, 3, 7, 20, 23, or 35;

i=14, j=0, 12, 15, 16, 17, 21, or 36;

i=15, j=0, 1, 10, 13, 18, 25, or 37;

i=16, j=1, 3, 11, 20, 22, or 38;

i=17, j=0, 14, 16, 17, 21, or 39;

i=18, j=1, 12, 13, 18, 19, or 40;

i=19, j=0, 1, 7, 8, 10, or 41;

i=20, j=0, 3, 9, 11, 22, or 42;

i=21, j=1, 5, 16, 20, 21, or 43;

i=22, j=0, 12, 13, 17, or 44;

i=23, j=1, 2, 10, 18, or 45;

i=24, j=0, 3, 4, 11, 22, or 46;

i=25, j=1, 6, 7, 14, or 47;

i=26, j=0, 2, 4, 15, or 48;

i=27, j=1, 6, 8, or 49;

i=28, j=0, 4, 19, 21, or 50;

i=29, j=1, 14, 18, 25, or 51;

i=30, j=0, 10, 13, 24, or 52;

i=31, j=1, 7, 22, 25, or 53;

i=32, j=0, 12, 14, 24, or 54;

i=33, j=1, 2, 11, 21, or 55;

i=34, j=0, 7, 15, 17, or 56;

i=35, j=1, 6, 12, 22, or 57;

i=36, j=0, 14, 15, 18, or 58;

i=37, j=1, 13, 23, or 59;

i=38, j=0, 9, 10, 12, or 60;

i=39, j=1, 3, 7, 19, or 61;

i=40, j=0, 8, 17, or 62;

i=41, j=1, 3, 9, 18, or 63;

i=42, j=0, 4, 24, or 64;

i=43, j=1, 16, 18, 25, or 65;

i=44, j=0, 7, 9, 22, or 66;

i=45, j=1, 6, 10, or 67;

wherein i is a row index of the LDPC base graph, 0≤i<46, j is a column index of the LDPC base graph, 0≤j<68.

3. The device according to claim 2 , wherein in obtaining the encoding matrix H by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns, the processor is configured to:

replace each element of value 0 in the LDPC base graph with an all zero matrix of Z rows×Z columns; and

replace a {row index i, column index j} element of value 1 in the LDPC base graph by a circular permutation matrix I(P i,j ) of Z rows×Z columns, wherein the circular permutation matrix I(P i,j ) is obtained by circularly shifting an identity matrix of Z rows×Z columns to the right P i,j times, wherein P i,j =mod (V i,j , Z), V i,j is a shift value corresponding to a lifting factor set index of Z, V i,j is an integer, and V i,j ≥0.

4. The device according to claim 1 , wherein K=22×Z.

5. The device according to claim 1 , wherein the input sequence is c={c 0 , c 1 , c 2 , . . . , c K−1 }, the encoded sequence is d={d 0 , d 1 , d 2 , . . . , d N−1 }, wherein c i (i=0, 1, . . . K−1) are information bits, d j (j=0, 1, . . . N−1) are encoded bits, N is a positive integer, and N=66×Z.

6. The device according to claim 5 , wherein the encoded sequence d comprises K 0 bits obtained from the input sequence c and N−K 0 parity bits in a parity sequence w={w 0 , w 1 , w 2 , . . . , w N−K 0 −1 }, K 0 is an integer greater than 0 and less than or equal to K, wherein the parity sequence w and the input sequence c meet:

H

×

[

c

T

w

T

]

=

0

T

,

wherein c T =[c 0 , c 1 , c 2 , . . . , c K−1 ] T is a transposed vector including bits in the input sequence, w T =[w 0 , w 1 , w 2 , . . . , w N−L 0 −1 ] T is a transposed vector including bits in the parity sequence, 0 T is a column vector, and values of all elements of 0 T are zero.

7. The device according to claim 6 , wherein K 0 =K−2×Z.

8. An apparatus in a communication device, comprising:

a processor and a memory storing program instructions;

wherein the processor, by executing the program instructions, is configured to:

obtain an input sequence, wherein the input sequence comprises K bits of information, and K is a positive integer;

determine a lifting factor Z according to K;

encode the input sequence using an encoding matrix H, to obtain an encoded sequence; and

output the encoded sequence;

wherein the encoding matrix H is obtained from a low density parity check (LDPC) base graph by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns;

wherein the LDPC base graph comprises m rows and n columns, 5≤m≤46, and 27≤n≤68, and each element in the LDPC base graph has a value of 0 or 1;

wherein an element in the LDPC base graph has a value of 1 when:

i=0, j=0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, or 23;

i=1, j=0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, or 24;

i=2, j=0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, or 25;

i=3, j=0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, or 25;

i=4, j=0, 1, or 26;

wherein i is a row index of the LDPC base graph, 0≤i<m, j is a column index of the LDPC base graph, 0≤j<n.

9. The apparatus according to claim 8 , wherein the LDPC base graph comprises 46 rows and 68 columns, and wherein an element in the LDPC base graph has the value of 1 when:

i=0, j=0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, or 23;

i=1, j=0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, or 24;

i=2, j=0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, or 25;

i=3, j=0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, or 25;

i=4, j=0, 1, or 26;

i=5, j=0, 1, 3, 12, 16, 21, 22, or 27;

i=6, j=0, 6, 10, 11, 13, 17, 18, 20, or 28;

i=7, j=0, 1, 4, 7, 8, 14, or 29;

i=8, j=0, 1, 3, 12, 16, 19, 21, 22, 24, or 30;

i=9, j=0, 1, 10, 11, 13, 17, 18, 20, or 31;

i=10, j=1, 2, 4, 7, 8, 14, or 32;

i=11, j=0, 1, 12, 16, 21, 22, 23, or 33;

i=12, j=0, 1, 10, 11, 13, 18, or 34;

i=13, j=0, 3, 7, 20, 23, or 35;

i=14, j=0, 12, 15, 16, 17, 21, or 36;

i=15, j=0, 1, 10, 13, 18, 25, or 37;

i=16, j=1, 3, 11, 20, 22, or 38;

i=17, j=0, 14, 16, 17, 21, or 39;

i=18, j=1, 12, 13, 18, 19, or 40;

i=19, j=0, 1, 7, 8, 10, or 41;

i=20, j=0, 3, 9, 11, 22, or 42;

i=21, j=1, 5, 16, 20, 21, or 43;

i=22, j=0, 12, 13, 17, or 44;

i=23, j=1, 2, 10, 18, or 45;

i=24, j=0, 3, 4, 11, 22, or 46;

i=25, j=1, 6, 7, 14, or 47;

i=26, j=0, 2, 4, 15, or 48;

i=27, j=1, 6, 8, or 49;

i=28, j=0, 4, 19, 21, or 50;

i=29, j=1, 14, 18, 25, or 51;

i=30, j=0, 10, 13, 24, or 52;

i=31, j=1, 7, 22, 25, or 53;

i=32, j=0, 12, 14, 24, or 54;

i=33, j=1, 2, 11, 21, or 55;

i=34, j=0, 7, 15, 17, or 56;

i=35, j=1, 6, 12, 22, or 57;

i=36, j=0, 14, 15, 18, or 58;

i=37, j=1, 13, 23, or 59;

i=38, j=0, 9, 10, 12, or 60;

i=39, j=1, 3, 7, 19, or 61;

i=40, j=0, 8, 17, or 62;

i=41, j=1, 3, 9, 18, or 63;

i=42, j=0, 4, 24, or 64;

i=43, j=1, 16, 18, 25, or 65;

i=44, j=0, 7, 9, 22, or 66;

i=45, j=1, 6, 10, or 67;

wherein i is a row index of the LDPC base graph, 0≤i<46, j is a column index of the LDPC base graph, 0≤j<68.

10. The apparatus according to claim 9 , wherein in obtaining the encoding matrix H by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns, the processor is configured to:

replace each element of value 0 in the LDPC base graph with an all zero matrix of Z rows×Z columns; and

replace a {row index i, column index j} element of value 1 in the LDPC base graph by a circular permutation matrix I(P i,j ) of Z rows×Z columns, wherein the circular permutation matrix I(P i,j ) is obtained by circularly shifting an identity matrix of Z rows×Z columns to the right P i,j times, wherein P i,j =mod (V i,j , Z), V i,j is a shift value corresponding to a lifting factor set index of Z, V i,j is an integer, and V i,j ≥0.

11. The apparatus according to claim 8 , wherein K=22×Z.

12. The apparatus according to claim 8 , wherein the input sequence is c={c 0 , c 1 , c 2 , . . . , c K−1 }, the encoded sequence is d={d 0 , d 1 , d 2 , . . . , d M−1 }, wherein c i (i=0, 1, . . . K−1) are information bits, d i (j=0, 1, . . . N−1) are encoded bits, wherein N is a positive integer, and N=66×Z.

13. The apparatus according to claim 12 , wherein the encoded sequence d comprises K 0 bits obtained from the input sequence c and N−K 0 parity bits in a parity sequence w={w 0 , w 1 , w 2 , . . . , w N−K 0 −1 }, K 0 is an integer greater than 0 and less than or equal to K,

wherein the parity sequence w and the input sequence c meet:

H

×

[

c

T

w

T

]

=

0

T

,

wherein c T =[c 0 , c 1 , c 2 , . . . , c K−1 ] T is a transposed vector including bits in the input sequence, w T =[w 0 , w 1 , w 2 , . . . , w N−K 0 −1 ] T is a transposed vector including bits in the parity sequence, 0 T is a column vector, and values of all elements of 0 T are zero.

14. The apparatus according to claim 13 , wherein K 0 =K−2×Z.

15. The apparatus to claim 8 , wherein the communication device is a network device or a terminal device in a communication network.

16. A microchip, comprising one or more integrated circuits that are configured to:

obtain an input sequence, wherein the input sequence comprises K bits of information, and K is a positive integer;

determine a lifting factor Z according to K;

encode the input sequence using an encoding matrix H, to obtain an encoded sequence; and

output the encoded sequence;

wherein the encoding matrix H is obtained from a low density parity check (LDPC) base graph by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns;

wherein the LDPC base graph comprises m rows and n columns, and 5≤m≤46, and 27≤n≤68,

and each element in the LDPC base graph has a value of 0 or 1;

wherein an element in the LDPC base graph has a value of 1 when:

i=0, j=0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, or 23;

i=1, j=0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, or 24;

i=2, j=0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, or 25;

i=3, j=0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, or 25;

i=4, j=0, 1, or 26;

wherein i is a row index of the LDPC base graph, 0≤i<m, j is a column index of the LDPC base graph, 0≤j<n.

17. The microchip according to claim 16 , wherein the LDPC base graph comprises 46 rows and 68 columns, and wherein an element in the LDPC base graph has the value of 1 when:

i=0, j=0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, or 23;

i=1, j=0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, or 24;

i=2, j=0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, or 25;

i=3, j=0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, or 25;

i=4, j=0, 1, or 26;

i=5, j=0, 1, 3, 12, 16, 21, 22, or 27;

i=6, j=0, 6, 10, 11, 13, 17, 18, 20, or 28;

i=7, j=0, 1, 4, 7, 8, 14, or 29;

i=8, j=0, 1, 3, 12, 16, 19, 21, 22, 24, or 30;

i=9, j=0, 1, 10, 11, 13, 17, 18, 20, or 31;

i=10, j=1, 2, 4, 7, 8, 14, or 32;

i=11, j=0, 1, 12, 16, 21, 22, 23, or 33;

i=12, j=0, 1, 10, 11, 13, 18, or 34;

i=13, j=0, 3, 7, 20, 23, or 35;

i=14, j=0, 12, 15, 16, 17, 21, or 36;

i=15, j=0, 1, 10, 13, 18, 25, or 37;

i=16, j=1, 3, 11, 20, 22, or 38;

i=17, j=0, 14, 16, 17, 21, or 39;

i=18, j=1, 12, 13, 18, 19, or 40;

i=19, j=0, 1, 7, 8, 10, or 41;

i=20, j=0, 3, 9, 11, 22, or 42;

i=21, j=1, 5, 16, 20, 21, or 43;

i=22, j=0, 12, 13, 17, or 44;

i=23, j=1, 2, 10, 18, or 45;

i=24, j=0, 3, 4, 11, 22, or 46;

i=25, j=1, 6, 7, 14, or 47;

i=26, j=0, 2, 4, 15, or 48;

i=27, j=1, 6, 8, or 49;

i=28, j=0, 4, 19, 21, or 50;

i=29, j=1, 14, 18, 25, or 51;

i=30, j=0, 10, 13, 24, or 52;

i=31, j=1, 7, 22, 25, or 53;

i=32, j=0, 12, 14, 24, or 54;

i=33, j=1, 2, 11, 21, or 55;

i=34, j=0, 7, 15, 17, or 56;

i=35, j=1, 6, 12, 22, or 57;

i=36, j=0, 14, 15, 18, or 58;

i=37, j=1, 13, 23, or 59;

i=38, j=0, 9, 10, 12, or 60;

i=39, j=1, 3, 7, 19, or 61;

i=40, j=0, 8, 17, or 62;

i=41, j=1, 3, 9, 18, or 63;

i=42, j=0, 4, 24, or 64;

i=43, j=1, 16, 18, 25, or 65;

i=44, j=0, 7, 9, 22, or 66;

i=45, j=1, 6, 10, or 67;

wherein i is a row index of the LDPC base graph, 0≤i<46, j is a column index of the LDPC base graph, 0≤j<68.

18. The microchip according to claim 16 , wherein in obtaining the encoding matrix H by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns, the one or more one or more integrated circuits are configured to:

replace each element of value 0 in the LDPC base graph with an all zero matrix of Z rows×Z columns; and

replace a {row index i, column index j} element of value 1 in the LDPC base graph by a circular permutation matrix I(P i,j ) of Z rows×Z columns, wherein the circular permutation matrix I(P i,j ) is obtained by circularly shifting an identity matrix of Z rows×Z columns to the right P i,j times, wherein P i,j =mod (V i,j , Z), V i,j is a shift value corresponding to a lifting factor set index of Z, V i,j is an integer, and V i,j ≥0.

19. The microchip according to claim 16 , wherein K=22×Z.

20. The microchip according to claim 16 , wherein the input sequence is c={c 0 , c 1 , c 2 , . . . , c K−1 }, the encoded sequence is d={d 0 , d 1 , d 2 , . . . , d N−1 }, wherein c i (i=0, 1, . . . K−1) are information bits, d j (j=0, 1, . . . N−1) are encoded bits, wherein N is a positive integer, and N=66×Z.

21. The microchip according to claim 20 , wherein the encoded sequence d comprises K 0 bits obtained from the input sequence c and N−K 0 parity bits in a parity sequence w={w 0 , w 1 , w 2 , . . . , w N−K 0 −1 }, K 0 is an integer greater than 0 and less than or equal to K,

wherein the parity sequence w and the input sequence c meet:

H

×

[

c

T

w

T

]

=

0

T

,

wherein c T =[c 0 , c 2 , c 2 , . . . , c K−1 ] T is a transposed vector including bits in the input sequence, w T =[w 0 , w 1 , w 2 , . . . , w N−K 0 −1 ] T is a transposed vector including bits in the parity sequence, 0 T is a column vector, and values of all elements of 0 T are zero.

22. The microchip according to claim 21 , wherein K 0 =K−2×Z.

23. A method for processing information, performed by a communication apparatus in a wireless network, comprising:

obtaining an input sequence, wherein the input sequence comprises K bits of information, and K is a positive integer;

determining a lifting factor Z according to K;

encoding the input sequence using an encoding matrix H, to obtain an encoded sequence; and

outputting the encoded sequence;

wherein the encoding matrix H is obtained from a low density parity check (LDPC) base graph by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns;

wherein the LDPC base graph comprises m rows and n columns, 5≤m≤46, and 27≤n≤68, and each element in the LDPC base graph has a value of 0 or 1;

wherein an element in the LDPC base graph has a value of 1 when:

i=0, j=0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, or 23;

i=1, j=0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, or 24;

i=2, j=0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, or 25;

i=3, j=0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, or 25;

i=4, j=0, 1, or 26;

wherein i is a row index of the LDPC base graph, 0≤i<46, j is a column index of the LDPC base graph, 0≤j<68.

24. The method according to claim 23 , wherein the LDPC base graph comprises 46 rows and 68 columns, and wherein an element in the LDPC base graph has the value of 1 when:

i=0, j=0, 1, 2, 3, 5, 6, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20, 21, 22, or 23;

i=1, j=0, 2, 3, 4, 5, 7, 8, 9, 11, 12, 14, 15, 16, 17, 19, 21, 22, 23, or 24;

i=2, j=0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 17, 18, 19, 20, 24, or 25;

i=3, j=0, 1, 3, 4, 6, 7, 8, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 22, or 25;

i=4, j=0, 1, or 26;

i=5, j=0, 1, 3, 12, 16, 21, 22, or 27;

i=6, j=0, 6, 10, 11, 13, 17, 18, 20, or 28;

i=7, j=0, 1, 4, 7, 8, 14, or 29;

i=8, j=0, 1, 3, 12, 16, 19, 21, 22, 24, or 30;

i=9, j=0, 1, 10, 11, 13, 17, 18, 20, or 31;

i=10, j=1, 2, 4, 7, 8, 14, or 32;

i=11, j=0, 1, 12, 16, 21, 22, 23, or 33;

i=12, j=0, 1, 10, 11, 13, 18, or 34;

i=13, j=0, 3, 7, 20, 23, or 35;

i=14, j=0, 12, 15, 16, 17, 21, or 36;

i=15, j=0, 1, 10, 13, 18, 25, or 37;

i=16, j=1, 3, 11, 20, 22, or 38;

i=17, j=0, 14, 16, 17, 21, or 39;

i=18, j=1, 12, 13, 18, 19, or 40;

i=19, j=0, 1, 7, 8, 10, or 41;

i=20, j=0, 3, 9, 11, 22, or 42;

i=21, j=1, 5, 16, 20, 21, or 43;

i=22, j=0, 12, 13, 17, or 44;

i=23, j=1, 2, 10, 18, or 45;

i=24, j=0, 3, 4, 11, 22, or 46;

i=25, j=1, 6, 7, 14, or 47;

i=26, j=0, 2, 4, 15, or 48;

i=27, j=1, 6, 8, or 49;

i=28, j=0, 4, 19, 21, or 50;

i=29, j=1, 14, 18, 25, or 51;

i=30, j=0, 10, 13, 24, or 52;

i=31, j=1, 7, 22, 25, or 53;

i=32, j=0, 12, 14, 24, or 54;

i=33, j=1, 2, 11, 21, or 55;

i=34, j=0, 7, 15, 17, or 56;

i=35, j=1, 6, 12, 22, or 57;

i=36, j=0, 14, 15, 18, or 58;

i=37, j=1, 13, 23, or 59;

i=38, j=0, 9, 10, 12, or 60;

i=39, j=1, 3, 7, 19, or 61;

i=40, j=0, 8, 17, or 62;

i=41, j=1, 3, 9, 18, or 63;

i=42, j=0, 4, 24, or 64;

i=43, j=1, 16, 18, 25, or 65;

i=44, j=0, 7, 9, 22, or 66;

i=45, j=1, 6, 10, or 67;

wherein i is a row index of the LDPC base graph, 0≤i<46, j is a column index of the LDPC base graph, 0≤j<68.

25. The method according to claim 24 , wherein obtaining the encoding matrix H by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns comprises:

replacing each element of value 0 in the LDPC base graph with an all zero matrix of Z rows×Z columns; and

replacing a {row index i, column index j} element of value 1 in the LDPC base graph by a circular permutation matrix I(P i,j ) of Z rows×Z columns, wherein the circular permutation matrix I(P i,j ) is obtained by circularly shifting an identity matrix of Z rows×Z columns to the right P i,j times, wherein P i,j =mod (V i,j , Z), V i,j is a shift value corresponding to a lifting factor set index of Z, V i,j is an integer, and V i,j ≥0.

26. The method according to claim 23 , wherein K=22×Z.

27. The method according to claim 23 , wherein the input sequence is c={c 0 , c 1 , c 2 , . . . , c K−1 }, the encoded sequence is d={d 0 , d 1 , d 2 , . . . , d N−1 }, wherein c i (i=0, 1, . . . K−1) are information bits, d j (j=0, 1, . . . N−1) are encoded bits, N is a positive integer, and N=66×Z.

28. The method according to claim 27 , wherein the encoded sequence d comprises K 0 bits obtained from the input sequence c and N−K 0 parity bits in a parity sequence w={w 0 , w 1 , w 2 , . . . , w N−K 0 −1 }, K 0 is an integer greater than 0 and less than or equal to K, wherein the parity sequence w and the input sequence c meet:

H

×

[

c

T

w

T

]

=

0

T

,

wherein c T =[c 0 , c 1 , c 2 , . . . , c K−1 ] T is a transposed vector including bits in the input sequence, w T =[w 0 , w 1 , w 2 , . . . , w N−L 0 −1 ] T is a transposed vector including bits in the parity sequence, 0 T is a column vector, and values of all elements of 0 T are zero.

29. The method according to claim 28 , wherein K 0 =K−2×Z.