Mask generation using reduction operators and scatter use thereof
Novel instructions, their format, and support thereof are described. For example, an instruction including a field for an opcode to indicate a reduction-based mask generation operation is to be performed, a field to identify a first packed data source operand, a field to identify a second packed data source operand, and a field to identify a destination operand to store reduction-based generated mask and its hardware support is described.
1. An apparatus comprising:
decode circuitry to decode a single instruction, the instruction including a field for an opcode to indicate a reduction-based mask generation operation is to be performed, a field to identify a first packed data source operand, a field to identify a second packed data source operand, and a field to identify a destination operand to store reduction-based generated mask;
execution circuitry to execute the decoded instruction according to a reduction operation specified by the instruction by determining whether there are conflicts between data elements of the identified first packed data source operand and for each data element position where there is not a conflict, setting a corresponding data element position in the identified destination operand; and for each conflict, applying the reduction operation to data elements of corresponding data elements of the identified second packed data source operand to determine which data element position to set in the identified destination operand and setting said position.
2. The apparatus of claim 1 , wherein the reduction operation is determined by an immediate value of the instruction.
3. The apparatus of claim 1 , wherein the reduction operation is determined by the opcode of the instruction.
4. The apparatus of claim 1 , further comprising:
the execution circuitry to update the identified second packed data source operand according to the reduction operation.
5. The apparatus of claim 1 , wherein the reduction operation is one of minimum, maximum, or arithmetic.
6. The apparatus of claim 1 , wherein the identified first and second packed data source operands are registers.
7. The apparatus of claim 1 , wherein the identified destination operand is a writemask register.
8. A method comprising:
decoding a single instruction, the instruction including a field for an opcode to indicate a reduction-based mask generation operation is to be performed, a field to identify a first packed data source operand, a field to identify a second packed data source operand, and a field to identify a destination operand to store reduction-based generated mask;
executing the decoded instruction according to a reduction operation specified by the instruction by determining whether there are conflicts between data elements of the identified first packed data source operand and for each data element position where there is not a conflict, setting a corresponding data element position in the identified destination operand; and for each conflict, applying the reduction operation to data elements of corresponding data elements of the identified second packed data source operand to determine which data element position to set in the identified destination operand and setting said position.
9. The method of claim 8 , wherein the reduction operation is determined by an immediate value of the instruction.
10. The method of claim 8 , wherein the reduction operation is determined by the opcode of the instruction.
11. The method of claim 8 , further comprising:
updating the identified second packed data source operand according to the reduction operation.
12. The method of claim 8 , wherein the reduction operation is one of minimum, maximum, or arithmetic.
13. The method of claim 8 , wherein the identified first and second packed data source operands are registers.
14. The method of claim 8 , wherein the identified destination operand is a writemask register.
15. A non-tangible machine-readable storage medium storing an instruction that is to cause a processor to perform a method comprising: decoding a single instruction, the instruction including a field for an opcode to indicate a reduction-based mask generation operation is to be performed, a field to identify a first packed data source operand, a field to identify a second packed data source operand, and a field to identify a destination operand to store reduction-based generated mask; executing the decoded instruction according to a reduction operation specified by the instruction by determining whether there are conflicts between data elements of the identified first packed data source operand and for each data element position where there is not a conflict, setting a corresponding data element position in the identified destination operand; and for each conflict, applying the reduction operation to data elements of corresponding data elements of the identified second packed data source operand to determine which data element position to set in the identified destination operand and setting said position.
16. The method of claim 8 , wherein the reduction operation is determined by an immediate value of the instruction.
17. The non-tangible machine-readable storage medium of claim 15 , wherein the reduction operation is determined by the opcode of the instruction.
18. The non-tangible machine-readable storage medium of claim 15 , further comprising:
updating the identified second packed data source operand according to the reduction operation.
19. The non-tangible machine-readable storage medium of claim 15 , wherein the reduction operation is one of minimum, maximum, or arithmetic.
20. The non-tangible machine-readable storage medium of claim 15 , wherein the identified first and second packed data source operands are registers.
21. An apparatus comprising:
decode circuitry to decode an instruction, the instruction including a field for an opcode to indicate a reduction-based scatter operation is to be performed, a field to identify a first packed data source operand, a field to identify a second packed data source operand, one or more fields to be used to generate one or more destination addresses;
execution circuitry to execute the decoded instruction according to a reduction operation specified by the instruction to scatter to memory data elements of selected data element positions of the identified second packed data source operand using index values of the identified first packed data source operand according to a mask generated by determining whether there are conflicts between data elements of the identified first packed data source operand and 1) for each data element position where there is not a conflict setting a corresponding data element position in the identified destination operand; 2) for each conflict, applying a reduction operation indicated by the opcode to data elements of corresponding data elements of the identified second packed data source operand to determine which data element position to set in the identified destination operand and setting said position; and 3) scattering data elements of the updated identified second packed data source operand at addresses generated using masked indices of the first packed data source operand.
22. The apparatus of claim 21 , wherein the addresses are generated using scale, index, and base (SIB) addressing, wherein and index of the sib address is determined by applying the generated mask to the indices of the first packed data source operand.
23. The apparatus of claim 22 , further comprising:
the execution circuitry to update the identified second packed data source operand according to the reduction operation.
24. The apparatus of claim 21 , wherein the reduction operation is determined by an immediate value of the instruction.
25. The apparatus of claim 21 , wherein the reduction operation is determined by the opcode of the instruction.
26. The apparatus of claim 21 , wherein the reduction operation is one of minimum, maximum, or arithmetic.
27. The apparatus of claim 21 , wherein the identified first and second packed data source operands are registers.
28. The apparatus of claim 21 , wherein the identified destination operand is a writemask register.
29. A method comprising:
decoding an instruction, the instruction including a field for an opcode to indicate a reduction-based scatter operation is to be performed, a field to identify a first packed data source operand, a field to identify a second packed data source operand, one or more fields to be used to generate one or more destination addresses;
executing the decoded instruction according to a reduction operation specified by the instruction to scatter to memory data elements of selected data element positions of the identified second packed data source operand using index values of the identified first packed data source operand according to a mask generated by determining whether there are conflicts between data elements of the identified first packed data source operand and 1) for each data element position where there is not a conflict setting a corresponding data element position in the identified destination operand; 2) for each conflict, applying a reduction operation indicated by the opcode to data elements of corresponding data elements of the identified second packed data source operand to determine which data element position to set in the identified destination operand and setting said position; and 3) scattering data elements of the updated identified second packed data source operand at addresses generated using masked indices of the first packed data source operand.
30. The method of claim 29 , wherein the addresses are generated using scale, index, and base (SIB) addressing, wherein and index of the sib address is determined by applying the generated mask to the indices of the first packed data source operand.
31. The method of claim 29 , further comprising:
updating the identified second packed data source operand according to the reduction operation.
32. The method of claim 29 , wherein the reduction operation is determined by an immediate value of the instruction.
33. The method of claim 29 , wherein the reduction operation is determined by the opcode of the instruction.
34. The method of claim 29 , wherein the reduction operation is one of minimum, maximum, or arithmetic.
35. The method of claim 29 , wherein the identified first and second packed data source operands are registers.
36. The method of claim 29 , wherein the identified destination operand is a writemask register.
37. A non-tangible machine-readable storage medium storing an instruction that is to cause a processor to perform a method according to any of claims 29 - 36 .