Conditional shader for graphics
An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.
1. An electronic processing system, comprising:
an application processor;
persistent storage media communicatively coupled to the application processor; and
a graphics subsystem communicatively coupled to the application processor, wherein the graphics subsystem includes:
a conditional shader wherein the conditional shader comprises: a thread analyzer to determine if a set of threads meet a thread condition; and a conditional kernel loader to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition, wherein the conditional shader is split into two invocations to:
determine, in the first invocation of the conditional shader, if one or more processing elements meet a condition associated with an execution unit instruction set that includes single instruction multiple data (SIMD) instructions, wherein the single instruction multiple data (SIMD) instructions support parallel execution of a plurality of threads even in the absence of multiple independent instruction units, wherein the condition is whether one or more pixels of the processing elements survives or not; and
process, in the second invocation of the conditional shader, the one or more processing elements based on whether the one or more processing elements are determined to meet the condition, wherein the surviving pixels are passed to parallel execution via the single instruction multiple data (SIMD) instructions only when the given pixel survives; and
a pixel regrouper communicatively coupled to the conditional shader to regroup the surviving pixels for parallel execution via the single instruction multiple data (SIMD) instructions, wherein the regroup operation is based on whether the one or more pixels are determined to meet the condition.
2. The system of claim 1 , wherein the condition comprises a visibility-type shader condition.
3. The system of claim 1 , wherein the condition pixel shader is further to:
determine if the one or more pixels meets a visibility-type shader condition.
4. The system of claim 3 , wherein the pixel regrouper is further to:
regroup the one or more pixels determined to meet the visibility-type shader condition for an instruction pipeline.
5. The system of claim 3 , wherein the condition pixel shader is further to:
determine if the one or more pixels are lit, and wherein the visibility-type shader condition comprises a lit-type shader condition.
6. The system of claim 5 , wherein the pixel regrouper is further to:
regroup the one or more pixels determined to be lit for a single instruction, multiple data pipeline.
7. A conditional shader apparatus, comprising:
a conditional pixel shader wherein the conditional pixel shader comprises: a thread analyzer to determine if a set of threads meet a thread condition; and a conditional kernel loader to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition, wherein the conditional pixel shader is split into two invocations to:
determine, in the first invocation of the conditional pixel shader, if one or more pixels meet a shader condition associated with an execution unit instruction set that includes single instruction multiple data (SIMD) instructions, wherein the single instruction multiple data (SIMD) instructions support parallel execution of a plurality of threads even in the absence of multiple independent instruction units, wherein the shader condition is whether any of the one or more pixels survives or not, and wherein the shader condition comprises a visibility-type shader condition;
process, in the second invocation of the conditional pixel shader, the surviving pixels based on whether the one or more processing elements are determined to meet the shader condition, and wherein the surviving pixels are passed to parallel execution via the single instruction multiple data (SIMD) instructions only when the given pixel survives; and
a pixel regrouper communicatively coupled to the conditional pixel shader to regroup the surviving pixels for parallel execution via the single instruction multiple data (SIMD) instructions, wherein the regroup operation is based on whether the one or more pixels are determined to meet the shader condition.
8. The apparatus of claim 7 , wherein the condition pixel shader is further to:
determine if the one or more pixels meets a visibility-type shader condition.
9. The apparatus of claim 8 , wherein the pixel regrouper is further to:
regroup the one or more pixels determined to meet the visibility-type shader condition for an instruction pipeline.
10. The apparatus of claim 8 , wherein the condition pixel shader is further to:
determine if the one or more pixels are lit, and wherein the visibility-type shader condition comprises a lit-type shader condition.
11. The apparatus of claim 10 , wherein the pixel regrouper is further to:
regroup the one or more pixels determined to be lit for a single instruction, multiple data pipeline.
12. A method of conditional shading, comprising:
determining if a set of threads meet a thread condition;
loading an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition;
splitting a conditional shader into a first and a second invocation to perform operations comprising:
determining, in a first invocation of the conditional shader, if one or more processing elements meet a condition associated with an execution unit instruction set that includes single instruction multiple data (SIMD) instructions, wherein the single instruction multiple data (SIMD) instructions support parallel execution of a plurality of threads even in the absence of multiple independent instruction units, wherein the condition is whether one or more pixels of the processing elements survives or not; and
processing, in a second invocation of the conditional shader, the one or more processing elements based on whether the one or more processing elements are determined to meet the condition, wherein the surviving pixels are passed to parallel execution via the single instruction multiple data (SIMD) instructions only when the given pixel survives; and
regrouping the surviving pixels for parallel execution via the single instruction multiple data (SIMD) instructions, wherein the regroup operation is based on whether the one or more pixels are determined to meet the condition.
13. The method of claim 12 , wherein the condition comprises a visibility-type shader condition.
14. The method of claim 12 , wherein the method further comprises:
determining if the one or more pixels meets a visibility-type shader condition.
15. The method of claim 14 , wherein the method further comprises:
regrouping the one or more pixels determined to meet the visibility-type shader condition for an instruction pipeline.
16. The method of claim 14 , wherein the method further comprises:
determining if the one or more pixels are lit, and wherein the visibility-type shader condition comprises a lit-type shader condition.
17. The method of claim 16 , wherein the method further comprises:
regrouping the one or more pixels determined to be lit for a single instruction, multiple data pipeline.