Shift register unit and driving method thereof, gate driving circuit and display panel
The disclosure relates to a shift register unit, a driving method of shift register units, a gate driving circuit and a display panel. The shift register unit includes: an input module, a pull-up module, a storage capacitor, an output module configured to transmit a first voltage signal to a signal output terminal under the control of the first voltage signal; and an output control module configured to transmit the first voltage signal or a second power signal to the signal output terminal under the control of the voltage signal of the pull-up node and a first selection signal, and to transmit the first voltage signal or the second power signal to the signal output terminal under the control of the voltage signal of the pull-up node and a second selection signal.
1. A shift register unit, comprising:
an input circuit, configured to transmit a first power signal to a pull-up node under control of an input signal;
a pull-up circuit, configured to transmit a clock signal to a first node under control of a voltage signal of the pull-up node;
a storage capacitor, connected between the pull-up node and the first node;
an output circuit, configured to transmit a first voltage signal to a signal output terminal under control of the first voltage signal; and
an output control circuit, configured to transmit the first voltage signal or a second power signal to the signal output terminal under control of the voltage signal of the pull-up node and a first selection signal, and to transmit the first voltage signal or the second power signal to the signal output terminal under control of the voltage signal of the pull-up node and a second selection signal,
wherein the output control circuit comprises;
a first switching element, having a control and connected to the pull-up node, a first end configured to receive the second power supply signal, and a second end connected to a first end of a second switching element;
a second switching element, having a control end configured to receive at least one of the first selection signal and the second selection signal, the first end connected to the second end of the first switching element, and a second end connected to a control end of a third switching element; and
the third switching element, having the control end connected to the second end of the s second switching element, a first end configured to receive the second power signal, and a second end connected to the signal output terminal.
2. The shift register unit according to claim 1 , wherein the output circuit comprises:
a fourth switching element, having a control end and a first end both configured to receive the first voltage signal, and a second end connected to a control end of a third switching element; and
a fifth switching element, having a control end and a first end both configured to receive the first voltage signal, and a second end connected to the signal output terminal.
3. The shift register unit according to claim 1 , further comprising:
a reset circuit, configured to transmit the second power signal to the pull-up node or to the first node under control of a reset signal; and
a noise reduction circuit, configured to transmit the second power signal to the first node under control of the first voltage signal.
4. The shift register unit according to claim 1 , wherein the input circuit comprises:
a sixth switching element, having a control end configured to receive the input signal, a first end configured to receive the first power signal, and a second end connected to the pull-up node.
5. The shift register unit according to claim 1 , wherein the pull-up circuit comprises:
a seventh switching element, having a control end connected to the pull-up node, a first end configured to receive the clock signal, and a second end connected to the first node.
6. The shift register unit according to claim 3 , wherein the noise reduction circuit comprises:
an eighth switching element, having a control end connected to the pull-up node, a first end configured to receive the second power signal, and a second end connected to a control end of a ninth switching element;
the ninth switching element, having the control end connected to the second end of the eighth switching element, a first end configured to receive the second power signal, and a second end connected to the first node; and
a tenth switching element, having a control end and a first terminal both configured to receive the first voltage signal, and a second end connected to the control end of the ninth switching element.
7. The shift register unit according to claim 3 , wherein the reset circuit comprising:
an eleventh switching element, having a control end configured to receive the reset signal, a first end configured to receive the second power signal, and a second end connected to the pull-up node; and
a twelfth switching element, having a control end configured to receive the reset signal, a first end configured to receive the second power signal, and a second end connected to the first node.
8. A gate driving circuit, comprising: a plurality of cascaded shift register units which comprises;
an input circuit, configured to transmit a first power signal to a pull-up node under control of an input signal;
a pull-up circuit, configured to transmit a clock signal to a first node under control of a voltage signal of the pull-up node;
a storage capacitor, connected between the pull-up node and the first node;
an output circuit, configured to transmit a first voltage signal to a signal output terminal under control of the first voltage signal; and
an output control circuit, configured to transmit the first voltage signal or a second power signal to the signal output terminal under control of the voltage signal of the pull-up node and a first selection signal, and to transmit the first voltage signal or the second power signal to the signal output terminal under control of the voltage signal of the pull-up node, and a second selection signal,
wherein,
an output signal of the signal output terminal of an Mth cascaded shift register unit is used as the input signal of an (M+3)th cascaded shift register unit; and
an output signal of the signal output terminal of the (M+3)th cascaded shift register unit is used as a reset signal of the Mth cascaded shift register unit.
9. The gate driving circuit according to claim 8 , wherein the clock signals of adjacent two rows of the cascaded shift register units having substantially inverse phases.
10. The gate driving circuit according to claim 8 , wherein a scanning mode of the gate driving circuit comprises a forward scanning, and the first power signal is at a logic high level, and the second power signal is at a logic low level.
11. The gate driving circuit according to claim 8 , wherein a scanning mode of the gate driving circuit comprises a reverse scanning, and the first power signal is at a logic low level, and the second power signal is at a logic high level.
12. A display panel, comprising a display area and a peripheral area; wherein the gate driving circuit according to claim 8 is provided in the peripheral area.
13. A driving method of shift register units, configured to drive the shift register unit which comprises;
an input circuit, configured to transmit a first power signal to a pull-up node under control of an input signal;
a pull-up circuit, configured to transmit a clock signal to a first node under control of a voltage signal of the pull-up node;
a storage capacitor, connected between the pull-up node and the first node;
an output circuit, configured to transmit a first voltage signal to a signal output terminal under control of the first voltage signal; and
an output control circuit, configured to transmit the first voltage signal or a second power signal to the signal output terminal under control of the voltage signal of the pull-up node and a first selection signal, and to transmit the first voltage signal or the second power signal to the signal output terminal under control of the voltage signal of the pull-up node, and a second selection signal,
wherein the method comprises;
when the first selection signal, the second selection signal, and the voltage signal of the pull-up node are all at a logic high level, transmitting the first voltage signal to the signal output terminal; and
when the first selection signal, the second selection signal, and/or the voltage signal of the pull-up node is at a logic low level, transmitting the second power signal to the signal output terminal.