Dual crystal orientation for semiconductor devices
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.
1. A semiconductor device, comprising:
a substrate;
a first fin structure comprising:
a first portion protruding from the substrate;
a second portion on a top surface of the first portion, the second portion comprising a dielectric layer; and
a third portion on a top surface of the second portion, wherein the third portion comprises a first material having a first top surface crystal orientation; and
a second fin structure comprising:
a fourth portion protruding from the substrate;
a fifth portion on a top surface of the fourth portion, wherein the fifth portion comprises a second material having a second top surface crystal orientation;
wherein the second material is different from the first material and the second top surface crystal orientation is different from the first top surface crystal orientation.
2. The semiconductor device of claim 1 , wherein the first material comprises silicon (Si) and the second material comprises silicon germanium (SiGe).
3. The semiconductor device of claim 1 , wherein the first top surface crystal orientation is (110) or (100) rotated 45-degree ((100) R45) and the second top surface crystal orientation is (100).
4. The semiconductor device of claim 1 ,
wherein the first material comprises Si and the first top surface crystal orientation comprises crystal orientation (110) or crystal orientation (100) R45; and
wherein the second material comprises SiGe and the second top surface crystal orientation comprises crystal orientation (100).
5. The semiconductor device of claim 1 , further comprising:
isolation structures formed over the substrate and on opposing sidewalls of the first and second fin structures; and
a gate structure formed over the first and second fin structures.
6. The semiconductor device of claim 1 , wherein the second fin structure comprises source/drain regions with p-type dopants; and
a buried channel region, between the source/drain regions with p-type dopants.
7. The semiconductor device of claim 6 , further comprising an n-type well with n-type dopants, wherein the n-type well is in the substrate under the second fin structure.
8. The semiconductor device of claim 1 ,
wherein the first fin structure comprises a first channel region comprising Si;
wherein the second fin structure comprises a second channel region comprising SiGe; and
wherein a thickness of the first channel region is less than a thickness of the second channel region.
9. The semiconductor device of claim 1 , further comprising:
a liner layer on sidewalls of the first and second portions of the first fin structure; and
an oxide layer in contact with the third portion of the first fin structure and the liner layer.
10. The semiconductor device of claim 1 , wherein a top surface of the fourth portion is substantially coplanar with the top surface of the first portion.
11. The semiconductor device of claim 1 , further comprising a first diode formed on the substrate, comprising:
a third fin structure formed on the substrate;
a first silicon germanium layer formed on a top surface of the third fin structure; and
a first doped epitaxial region on the first silicon germanium layer, wherein the doped epitaxial region comprises the first material having the first top surface crystal orientation.
12. The semiconductor device of claim 11 , further comprising a second diode formed on the substrate, comprising:
a fourth fin structure formed on the substrate;
a second silicon germanium layer formed on a top surface of the fourth fin structure; and
a second doped epitaxial region on the second silicon germanium layer, wherein the second doped epitaxial region comprises the second material having the second top surface crystal orientation.
13. The semiconductor device of claim 12 , wherein top surfaces of the first and second doped epitaxial regions, the third portion of the first fin structure, and the fifth portion of the second fin structure are substantially coplanar.
14. The semiconductor device of claim 12 , further comprising an n-type well in contact with the first and second silicon germanium layers.
15. A semiconductor device comprising:
a substrate; and
a first fin field effect transistor (FinFET), a second FinFET, and a diode disposed on the substrate, wherein:
the first FinFET comprises:
a dielectric layer comprising top and bottom surfaces; and
a first fin structure on the top surface of the dielectric layer, wherein the first fin structure comprises a first material having a first top surface crystal orientation;
the second FinFET comprises a second fin structure with a second material having a second top surface crystal orientation, wherein:
the second fin structure comprising a bottom surface that is substantially coplanar with the bottom surface of the dielectric layer;
the second material is different from the first material; and
the second top surface crystal orientation is different from the first top surface crystal orientation; and
the diode comprises:
a third fin structure;
a silicon germanium layer formed on a top surface of the third fin structure; and
a doped epitaxial region on the silicon germanium layer, wherein the doped epitaxial region comprises the first material having the first top surface crystal orientation.
16. The semiconductor device of claim 15 , wherein the semiconductor device further comprises an n-type well in the substrate and under the first, second, and third fin structures.
17. The semiconductor device of claim 15 , wherein the bottom surfaces of the dielectric layer and the second fin structure are substantially coplanar.
18. The semiconductor device of claim 15 , further comprising an other diode, comprising:
a fourth fin structure;
an other silicon germanium layer formed on a top surface of the fourth fin structure; and
an other doped epitaxial region on the other silicon germanium layer, wherein the other doped epitaxial region comprises the second material having the second top surface crystal orientation.
19. A method of fabricating a semiconductor device, comprising:
forming a device layer and a dielectric layer formed on a top surface of a substrate;
removing a first portion of the device layer and a first portion of the dielectric layer exposing a portion of the substrate;
forming a silicon germanium (SiGe) epitaxy layer over the portion of the substrate;
depositing a polysilicon structure between the device layer and the SiGe epitaxy layer; and
etching the device layer, the dielectric layer, the SiGe epitaxy layer, and the substrate to form:
a first fin structure on a top surface of a second portion of the dielectric layer and comprising a second portion of the device layer, wherein the second portion of the device layer comprises a first top surface crystal orientation; and
a second fin structure on the top surface of the substrate and comprising a remaining portion of the SiGe epitaxy layer, wherein the second fin structure comprises a second top surface crystal orientation different from the first top surface crystal orientation.
20. The method of claim 19 , wherein a bottom surface of the second portion of the dielectric layer is substantially coplanar with a bottom surface of the second fin structure.