Transient voltage suppressor
A transient voltage suppressor is provided, comprising a heavily doped substrate connected to a first node, a first doped layer formed on the heavily doped substrate, a second doped layer formed on the first doped layer, a first heavily doped region and a second heavily doped region formed in the second doped layer and coupled to a second node, and a plurality of trenches arranged in the heavily doped substrate, having a depth not less than that of the first doped layer for electrical isolation. The heavily doped substrate, the second doped layer, and the second heavily doped region belong to a first conductivity type. The first doped layer and the first heavily doped region belong to a second conductivity type. By employing the proposed present invention, pn junctions of the transient voltage suppressor can be controlled beneath the surface, thereby reducing the junction capacitance effectively.
1. A transient voltage suppressor, comprising:
a heavily doped substrate of a first conductivity type, which is connected to a first node;
a first doped layer of a second conductivity type, which is formed on said heavily doped substrate;
a second doped layer of said first conductivity type, which is formed on said first doped layer of said second conductivity type;
a first heavily doped region of said second conductivity type formed in said second doped layer and coupled to a second node;
a second heavily doped region of said first conductivity type formed in said second doped layer and coupled to said second node; and
a plurality of trenches arranged in said heavily doped substrate, having a depth not less than that of said first doped layer, wherein at least one of said plurality of trenches is disposed between said first heavily doped region and said second heavily doped region for electrical isolation, wherein when said first conductivity type is N type, said second conductivity type is P type, and said first node and said second node are coupled to an I/O pin and ground, respectively.
2. The transient voltage suppressor according to claim 1 , wherein said first doped layer of said second conductivity type is a P type epitaxial layer.
3. The transient voltage suppressor according to claim 2 , wherein said second doped layer of said first conductivity type is an N type epitaxial layer.
4. The transient voltage suppressor according to claim 2 , wherein said second doped layer of said first conductivity type is an N type lightly doped well.
5. The transient voltage suppressor according to claim 4 , wherein said second doped layer of said first conductivity type in which said first heavily doped region is formed can be alternatively removed such that said first heavily doped region is formed directly in said first doped layer of said second conductivity type.
6. A transient voltage suppressor, comprising:
a heavily doped substrate of a first conductivity type, which is connected to a first node;
a first doped layer of a second conductivity type, which is formed on said heavily doped substrate;
a second doped layer of said first conductivity type, which is formed on said first doped layer of said second conductivity type;
a first heavily doped region of said second conductivity type formed in said second doped layer and coupled to a second node;
a second heavily doped region of said first conductivity type formed in said second doped layer and coupled to said second node; and
a plurality of trenches arranged in said heavily doped substrate, having a depth not less than that of said first doped layer, wherein at least one of said plurality of trenches is disposed between said first heavily doped region and said second heavily doped region for electrical isolation, wherein when said first conductivity type is P type, said second conductivity type is N type, and said first node and said second node are coupled to ground and an I/O pin, respectively.
7. The transient voltage suppressor according to claim 6 , wherein said first doped layer of said second conductivity type is an N type epitaxial layer.
8. The transient voltage suppressor according to claim 7 , wherein said second doped layer of said first conductivity type is a P type epitaxial layer.
9. The transient voltage suppressor according to claim 7 , wherein said second doped layer of said first conductivity type is a P type lightly doped well.
10. The transient voltage suppressor according to claim 9 , wherein said second doped layer of said first conductivity type in which said first heavily doped region is formed can be alternatively removed such that said first heavily doped region is formed directly in said first doped layer of said second conductivity type.