Magnetic memory cell
A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.
1. A magnetic memory cell, comprising:
a substrate comprising an active area surrounded by an isolation region, wherein the active area protrudes from an upper surface of the isolation region;
a select transistor on the active area of the substrate;
a first dielectric layer disposed on the substrate, wherein the first dielectric layer covers the active area and the select transistor;
a landing pad in the first dielectric layer, wherein the landing pad is situated in a first horizontal plane and is electrically coupled to a drain region of the select transistor;
a second dielectric layer covering the first dielectric layer and the landing pad;
a memory stack in the second dielectric layer, wherein the memory stack comprises a bottom electrode electrically coupled to the landing pad and a top electrode electrically coupled to a bit line disposed above the second dielectric layer; and
a source line in the first dielectric layer, wherein the source line is situated in a second horizontal plane and is electrically coupled to a source region of the select transistor, wherein the second horizontal plane and the first horizontal plane are not coplanar.
2. The magnetic memory cell of claim 1 , wherein the second dielectric layer comprises a nitrogen-doped silicon carbide (NDC) layer, a silicon oxide layer on the NDC layer, and an ultra-low k material layer on the silicon oxide layer.
3. The magnetic memory cell of claim 2 further comprising a via plug disposed in the silicon oxide layer and the NDC layer.
4. The magnetic memory cell of claim 3 , wherein the via plug electrically connects the bottom electrode to the landing pad.
5. The magnetic memory cell of claim 3 , wherein the via plug is a tungsten via plug.
6. The magnetic memory cell of claim 1 , wherein the landing pad is in a first metal (M1) layer.
7. The magnetic memory cell of claim 6 , wherein the source line is in a zero metal (M0) layer and is in close proximity to the landing pad.
8. The magnetic memory cell of claim 7 , wherein the zero metal (M0) layer is a tungsten layer and the first metal (M1) layer is a damascened copper layer.
9. The magnetic memory cell of claim 1 further comprising a word line disposed on the substrate and electrically coupled to a gate of the select transistor, wherein the word line extends along a first direction.