Space deposition between source/drain and sacrificial layers
A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.
1. A method for manufacturing a vertical transistor device, comprising:
forming a fin on a semiconductor substrate;
forming sacrificial dielectric spacer layers on the fin;
removing portions of the semiconductor substrate located under the sacrificial dielectric spacer layers and located at sides of the fin;
forming doped bottom source/drain regions in at least part of an area where the portions of the semiconductor substrate were removed;
forming doped sacrificial semiconductor layers on the doped bottom source/drain regions;
diffusing dopants from the doped bottom source/drain regions and the doped sacrificial semiconductor layers into a portion of the semiconductor substrate under the fin;
removing the doped sacrificial semiconductor layers; and
forming bottom spacers in at least part of an area where the doped sacrificial semiconductor layers were removed;
wherein forming the bottom spacers comprises:
conformally depositing a bottom spacer layer on the doped bottom source/drain regions and in spaces between top surfaces of the doped bottom source/drain regions and bottom surfaces of the sacrificial dielectric spacer layers; and
etching back portions of the bottom spacer layer to expose portions of the top surfaces of the doped bottom source/drain regions; and
forming additional bottom spacers on lateral sides of the bottom spacers and on the exposed portions of the top surfaces of the doped bottom source/drain regions.
2. The method according to claim 1 , wherein top surfaces of the bottom spacers have a planar profile, and top surfaces of the additional bottom spacers have a concave shape.
3. A method for manufacturing a semiconductor device, comprising:
forming a plurality of fins on a semiconductor substrate;
forming sacrificial spacer layers on the plurality of fins;
removing portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins;
growing bottom source/drain regions in at least part of an area where the portions of the semiconductor substrate were removed;
growing sacrificial epitaxial layers on the bottom source/drain regions;
diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins;
removing the sacrificial epitaxial layers;
forming bottom spacers in at least part of an area where the sacrificial epitaxial layers were removed;
wherein forming the bottom spacers comprises:
conformally depositing a bottom spacer layer on the bottom source/drain regions and in spaces between top surfaces of the bottom source/drain regions and bottom surfaces of the sacrificial spacer layers; and
etching back portions of the bottom spacer layer to expose portions of the top surfaces of the bottom source/drain regions; and
forming additional bottom spacers on lateral sides of the bottom spacers and on the exposed portions of the top surfaces of the bottom source/drain regions.
4. The method according to claim 3 , wherein top surfaces of the bottom spacers have a planar profile.
5. The method according to claim 3 , further comprising removing the sacrificial spacer layers from the plurality of fins.
6. The method according to claim 3 , wherein:
the diffusion of the dopants converts the portions of the semiconductor substrate under the plurality of fins into source/drain junction regions; and
the bottom spacers are formed on lateral sides of the source/drain junction regions.
7. The method according to claim 3 , further comprising selectively removing the sacrificial spacer layers from the plurality of fins with respect to the bottom spacers and the additional bottom spacers.
8. The method according to claim 3 , further comprising forming gate structures on the bottom spacers and the additional bottom spacers, wherein the gate structures each comprise a dielectric layer and at least one metal layer.
9. The method according to claim 3 , wherein the sacrificial epitaxial layers comprise a higher concentration of germanium than the bottom source/drain regions.
10. The method according to claim 3 , wherein portions of the bottom spacer layer are pinched off in the spaces.
11. The method according to claim 10 , wherein the etching back patterns the bottom spacer layer into the bottom spacers, wherein the bottom spacers comprise the pinched off portions in the spaces.
12. The method according to claim 3 , wherein the removing of the portions of the semiconductor substrate comprises recessing the portions of the semiconductor substrate to different depths.
13. The method according to claim 3 , wherein top surfaces of the bottom spacers have a planar profile, and top surfaces of the additional bottom spacers have a concave shape.