IP Library Granted Patent US 10,930,813
Granted Patent B2
US 10,930,813 · App. 16/208,901 · Granted Feb 23, 2021

Semiconductor light-emitting array and method of manufacturing the same

Inventors: Junghun Park (Yongin-si, KR); Junhee Choi (Seongnam-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L33/007H01L27/156H01L33/08H01L33/20H01L33/32H01L33/48
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Quick Facts
Patent No.
US 10,930,813
App. No.
16/208,901
Granted
Feb 23, 2021
Kind
B2
Abstract

Provided are a semiconductor light-emitting array and a method of manufacturing the same. The manufacturing method includes forming a plurality of grooves in a region of a substrate and sequentially growing a first semiconductor layer, an active layer, and a second semiconductor layer on the substrate to form a light-emitting structure layer.

Claims (19)

1. A method of manufacturing a semiconductor light-emitting array, the manufacturing method comprising:

forming a plurality of first grooves on an upper surface of a substrate by a physical or a mechanical process; and

forming a light-emitting structure layer by sequentially growing a first semiconductor layer, an active layer, and a second semiconductor layer on the substrate;

forming a plurality of first electrodes respectively electrically connected to the first semiconductor layer and a plurality of second electrodes respectively electrically connected to the second semiconductor layer;

separating the light-emitting structure layer, the plurality of first electrodes and the plurality of second electrodes into units of semiconductor light-emitting device,

wherein each of the upper surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer comprises a plurality of second grooves corresponding to the plurality of first grooves and overlapping the plurality of first grooves in a one-to-one manner in a plan view, and

the plurality of first and second grooves do not overlap with the plurality of first and second electrodes in the plan view.

2. The method of claim 1 , wherein the plurality of first grooves are formed one-dimensionally or two-dimensionally.

3. The method of claim 1 , wherein the plurality of first grooves have point shapes and are spaced apart from one another.

4. The method of claim 1 , wherein the plurality of first grooves have linear shapes and are spaced apart from one another.

5. The method of claim 1 , wherein the plurality of first grooves have a mesh structure.

6. The method of claim 1 , wherein a thickness of the substrate is 10 mm or less.

7. The method of claim 1 , wherein a depth of the first grooves is 15 μm or less.

8. The method of claim 1 , wherein a maximum width of the first grooves is 15 μm or less.

9. The method of claim 1 , wherein the plurality of first grooves are formed by dicing or dry etching.

10. The method of claim 1 , wherein the light-emitting structure layer is formed by epitaxial growth.

11. The method of claim 1 , wherein the substrate is a sapphire substrate.

12. The method of claim 1 , wherein the light-emitting structure layer includes a nitride-based semiconductor material.

13. The method of claim 1 , wherein a non-grooved portion of at least one of the first semiconductor layer, the active layer, or the second semiconductor layer overlaps a non-grooved portion of the substrate in the plan view.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2018
From: PARK, JUNGHUN; CHOI, JUNHEE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 048325/0628 →
Priority Claims (1)
KR 10-2017-0165231 · Dec 4, 2017 · national
Continuity (1)
Related Publication 20190172969A1 · Jun 6, 2019
Cited By (1)
US 12,237,365