IP Library Granted Patent US 12,237,365
Granted Patent B2
US 12,237,365 · App. 18/456,069 · Granted Feb 25, 2025

Micro light-emitting display apparatus and method of manufacturing the same

Inventors: Junhee Choi (Seongnam-si, KR); Kiho Kong (Suwon-si, KR); Nakhyun Kim (Yongin-si, KR); Dongho Kim (Seoul, KR); Junghun Park (Yongin-si, KR); Jinjoo Park (Yongin-si, KR); Eunsung Lee (Seoul, KR); Joohun Han (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L27/156
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,237,365
App. No.
18/456,069
Granted
Feb 25, 2025
Kind
B2
Abstract

A micro light-emitting display apparatus and a method of manufacturing the same are disclosed The micro light-emitting display apparatus includes a first semiconductor layer, an isolation structure provided on the first semiconductor layer and configured to define a plurality of sub-pixels each configured to emit light, a first light-emitting unit including a first active layer provided in a first sub-pixel among the plurality of sub-pixels, and a second semiconductor layer provided on the first active layer, and a second light-emitting unit including a rod semiconductor layer provided in a second sub-pixel among the plurality of sub-pixels, a second active layer provided on the rod semiconductor layer, and a third semiconductor layer provided on the second active layer. The first active layer is configured to emit blue light and the second active layer is configured to emit green light.

Claims (30)

1. A method of manufacturing a micro light-emitting display apparatus, the method comprising:

forming a first active layer on a first semiconductor layer;

forming a second semiconductor layer on the first active layer;

forming a first isolation structure and a second isolation structure in the first active layers, the first isolation structure having a first width and the second isolation structure having a second width greater than the first width;

forming a first layer on the first active layer, the first isolation structure, and the second isolation structure;

exposing a first area of the second isolation structure;

forming a regrowth area by etching the exposed first area of the second isolation structure;

regrowing a semiconductor layer in the regrowth area;

planarizing the semiconductor layer to form a rod semiconductor layer;

forming a second active layer on the rod semiconductor layer; and

forming a third semiconductor layer on the second active layer.

2. The method of claim 1 , wherein, in the planarizing of the semiconductor layer, an etching solution including potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH) is used.

3. The method of claim 1 , wherein the rod semiconductor layer comprises a first portion having a constant width viewed along a height direction and a second portion where the width changes viewed along the height direction, wherein the second portion may include a first inclined surface, a second inclined surface facing the first inclined surface, and an upper surface between the first inclined surface and the second inclined surface.

4. The method of claim 3 , wherein an angle between a surface extending from the first inclined surface and the upper surface ranges from about 47 degrees to about 57 degrees.

5. The method of claim 3 , wherein a width D 1 of the upper surface satisfies the following equation: D 1 =D−2×(h 1 /tan β), where h 1 is a height of the second portion, β is an angle between the surface extending from the first inclined surface and the upper surface and D is a width of the first portion.

6. The method of claim 3 , wherein an aspect ratio (H/D) of the first portion satisfies 0.05<H/D<20, where H is a height of the first portion and D is a width of the first portion.

7. The method of claim 6 , wherein the height H of the first portion satisfies 0.5 μm<H<20 μm.

8. The method of claim 5 , wherein the height h 1 of the second portion is about 100 nm or less.

9. The method of claim 1 , wherein the display apparatus further includes a third light-emitting unit configured to emit red light.

10. The method of claim 9 , wherein the third light-emitting unit comprises a plurality of nanorod semiconductor layers arranged apart from each other on the first semiconductor layer, a third active layer, among a plurality of third active layers, provided on each of the plurality of nanorod semiconductor layers, and a fourth semiconductor layer, among a plurality of fourth semiconductor layer, provided on each of the third active layers.

11. The method of claim 10 , wherein each of the nanorod semiconductor layers and each of the third active layers have a width in a range of about 10 nm to about 100 nm.

12. The method of claim 10 , wherein a pitch between the nanorod semiconductor layers is in a range of about 20 nm to about 300 nm.

13. A method of manufacturing a micro light-emitting display apparatus, the method comprising:

forming a first active layer on a first semiconductor layer;

forming a second semiconductor layer on the first active layer;

forming an isolation structure in the first active layer and the second semiconductor layer;

etching an upper surface of the isolation structure to form an opening;

forming a rod semiconductor layer in the opening;

forming a second active layer on the rod semiconductor layer; and

forming a third semiconductor layer on the second active layer.

Priority Claims (1)
KR 10-2020-0128269 · Oct 5, 2020 · national
Continuity (2)
Continuation 17227981 · Apr 12, 2021
Related Publication 20230402493A1 · Dec 14, 2023
References Cited (22)
US 9978808B2 · Schneider, Jr. et al. · 2018 [cited by applicant]
US 10573684B2 · Schubert et al. · 2020 [cited by applicant]
US 10586829B2 · Yoo · 2020 [cited by applicant]
US 10930813B2 · Park et al. · 2021 [cited by applicant]
US 20090190371A1 · Root et al. · 2009 [cited by applicant]
US 20170323925A1 · Schneider, Jr. et al. · 2017 [cited by applicant]
US 20180351035A1 · Chung et al. · 2018 [cited by applicant]
US 20190214529A1 · Ahmed · 2019 [cited by applicant]
US 20200075801A1 · Chung et al. · 2020 [cited by applicant]
US 20200083405A1 · Choi et al. · 2020 [cited by applicant]
US 20200127173A1 · Park et al. · 2020 [cited by applicant]
US 20200135970A1 · Dasgupta · 2020 [cited by examiner]
US 20200168663A1 · Choi et al. · 2020 [cited by applicant]
US 20210226092A1 · Choi et al. · 2021 [cited by applicant]
US 20210391499A1 · Kim et al. · 2021 [cited by applicant]
US 20210399173A1 · Choi et al. · 2021 [cited by applicant]
JP 2019516251A · 2019 [cited by applicant]
KR 1020180133192A · 2018 [cited by applicant]
KR 1020190065752A · 2019 [cited by applicant]
Communication dated Jan. 4, 2022 issued by the European Patent Office in counterpart European Application No. 21180803.5. [cited by applicant]
Glas, F., “Critical dimensions for the plastic relaxation of strained axial heterostructures in free-standing nanowires”, Physical Review B, The American Physical Society, vol. 74, 2006, pp. 121302-1-121302-4 (4 pages). [cited by applicant]
Karpov, S., “Suppression of phase separation in InGaN due to elastic strain”, MRS Internet Journal Nitride Semiconductor Research, 1998, vol. 16, pp. 1-5 (6 pages). [cited by applicant]