Adjusting a throttling threshold in a processor

1. A processor comprising:

a plurality of processing cores to execute instructions; and

throttling logic to:

determine an average capacitance score for execution events in a sliding window;

perform frequency throttling when the average capacitance score exceeds a throttling threshold;

determine a count of frequency throttling instances; and

in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency.

2. The processor of claim 1 , the throttling logic to:

in response to a determination that the count of frequency throttling instances does not exceed the maximum throttling value:

reduce the throttling threshold and concurrently increase the baseline frequency in response to a determination that a currently executed application requires additional performance.

3. The processor of claim 2 , the throttling logic to:

in response to a determination that the count of frequency throttling instances does not exceed the maximum throttling value:

maintain the throttling threshold in response to a determination that the currently executed application does not require additional performance.

4. The processor of claim 1 , the throttling logic to:

detect the execution events in a first processing core;

determine capacitance values based on a plurality of capacitance weights associated with the detected execution events;

sum the capacitance values; and

divide the sum of capacitance values by a number of cycles in the sliding window to obtain the average capacitance score.

5. The processor of claim 4 , wherein the plurality of capacitance weights are adjusted based on bit widths of the detected execution events.

6. The processor of claim 1 , wherein the throttling threshold is one of a plurality of throttling thresholds, wherein at least some of the plurality of throttling thresholds are associated with distinct bit widths of the execution events.

7. The processor of claim 1 , wherein the throttling threshold is refreshed in response to an issuance of a maximum current protection (IccP) license to a first processing engine.

8. The processor of claim 1 , the throttling logic to balance an increase to the throttling threshold and a reduction to the baseline frequency based on an overall capacity of a power infrastructure supporting the processor.

9. A method, comprising:

calculating an average capacitance score for execution events in a first processor core;

determining whether the average capacitance score exceeds a throttling threshold;

throttling a frequency of the processor in response to a determination that the average capacitance score exceeds the throttling threshold;

determining a count of throttling events in the first processor core;

at a plurality of points in time, determining whether the count of throttling events exceeds a maximum throttling value; and

in response to a determination that the count of throttling events exceeds the maximum throttling value at a first point in time, increasing the throttling threshold.

10. The method of claim 9 , comprising:

in response to the determination that the count of throttling events exceeds the maximum throttling value at the first point in time, reducing a baseline frequency of the first processor core concurrently with increasing the throttling threshold.

11. The method of claim 9 , comprising:

in response to a determination that the count of throttling events does not exceed the maximum throttling value at the second point in time:

determining whether a first application requires additional performance; and

reducing the throttling threshold and concurrently increasing the baseline frequency in response to a determination that the first application requires additional performance.

12. The method of claim 11 , comprising:

in response to a determination that the count of throttling events does not exceed the maximum throttling value at the third point in time:

determining whether a second application requires additional performance; and

maintaining the throttling threshold and the baseline frequency in response to a determination that the second application does not require additional performance.

13. The method of claim 9 , comprising:

detecting the execution events in the first processor core;

determining capacitance values based on a plurality of capacitance weights associated with the detected execution events;

summing the capacitance values; and

dividing the sum of capacitance values by a number of cycles in a sliding window to obtain the average capacitance score.

14. The method of claim 13 , comprising:

adjusting the plurality of capacitance weights based on bit widths of the detected execution events.

15. The method of claim 9 , comprising:

refreshing the throttling threshold during an issuance of a maximum current protection (IccP) license to the first processor core.

16. A system comprising:

a processor comprising a plurality of cores to execute instructions, wherein a first core comprises a throttling circuit to:

determine an average capacitance score for execution events in the first core;

perform frequency throttling when the average capacitance score exceeds a throttling threshold;

determine a count of throttling instances; and

in response to a determination that the count of throttling instances exceeds a maximum throttling value, increase the throttling threshold; and

a system memory coupled to the processor.

17. The system of claim 16 , the throttling circuit to:

in response to the determination that the count of throttling instances exceeds the maximum throttling value, reduce a baseline frequency of the first core while increasing the throttling threshold.

18. The system of claim 16 , the throttling circuit to:

in response to a determination that the count of throttling instances does not exceed the maximum throttling value:

reduce the throttling threshold and concurrently increase the baseline frequency of the first core in response to a determination that an executed application requires additional performance.

19. The system of claim 18 , the throttling circuit to:

in response to a determination that the count of throttling instances does not exceed the maximum throttling value:

maintain the throttling threshold and a baseline frequency of the first core in response to a determination that the executed application does not require additional performance.

20. The system of claim 16 , the throttling circuit to:

detect the execution events in the first core;

determine capacitance values based on a plurality of capacitance weights associated with the execution events;

sum the capacitance values; and

divide the sum of capacitance values by a number of cycles in a sliding window to obtain the average capacitance score.