Microelectronic devices designed with ultra-high-k dielectric capacitors integrated with package substrates

1. A microelectronic device comprising:

a plurality of organic dielectric layers; and

a capacitor formed within at least one organic dielectric layer of the plurality of organic dielectric layers, and the capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes, wherein the capacitor further comprises a first seed layer that is disposed on the first conductive electrode and the ultra-high-k dielectric layer is disposed on the first seed layer, wherein the first seed layer comprises a conductive oxide layer.

2. The microelectronic device of claim 1 , wherein the capacitor has a capacitance density of at least 10 nanoFarad per millimeter.

3. The microelectronic device of claim 1 , wherein the ultra-high-k dielectric layer has a relative permittivity of at least 200 up to 10,000.

4. The microelectronic device of claim 1 , wherein the capacitor further comprises a second seed layer that is disposed on the ultra-high-k dielectric layer and the second conductive electrode is disposed on the second seed layer.

5. The microelectronic device of claim 1 , wherein the capacitor is formed within a single organic dielectric layer of the plurality of organic dielectric layers.

6. The microelectronic device of claim 1 , wherein each electrode of the capacitor is formed within a different single organic dielectric layer of the plurality of organic dielectric layers.

7. The microelectronic device of claim 1 , wherein each electrode of the capacitor is formed with an interdigitated configuration.

8. A microelectronic device comprising:

at least one organic dielectric layer of a package substrate; and

a capacitor that is formed within the at least one organic dielectric layer of the package substrate, and the capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes, wherein the capacitor further comprises a first seed layer that is disposed on the first conductive electrode and the ultra-high-k dielectric layer is disposed on the first seed layer, wherein the first seed layer comprises a conductive oxide layer.

9. The microelectronic device of claim 8 , wherein the capacitor has a capacitance density of at least 10 nanoFarad per millimeter 2 .

10. The microelectronic device of claim 8 , wherein the ultra-high-k dielectric layer has a relative permittivity of at least 200 up to 10,000.

11. The microelectronic device of claim 8 , wherein the capacitor further comprises a second seed layer that is disposed on the ultra-high-k dielectric layer and the second conductive electrode is disposed on the second seed layer.

12. A method to fabricate a capacitor comprising:

forming a first capacitor electrode layer within an organic dielectric layer of a package substrate;

sputtering a first seed layer on the first capacitor electrode layer, wherein the first seed layer comprises a conductive oxide layer; and

sputtering an ultra-high-k dielectric layer on the first seed layer.

13. The method of claim 12 , further comprising:

laser annealing the ultra-high-k dielectric layer in capacitor electrode regions to crystallize the ultra-high-k dielectric layer without damaging the organic dielectric layer of the package substrate.

14. The method of claim 13 , further comprising:

sputtering a second seed layer on the ultra-high-k dielectric layer;

forming a conductive layer on the second seed layer.

15. The method of claim 14 , further comprising:

performing a lithographic operation and plating of a conductive layer in the capacitor electrode regions to form a second capacitor electrode; and

utilizing the second capacitor electrode as a hard mask for etching regions of the second seed layer, regions of the ultra-high-k dielectric layer, and regions of the first seed layer to form the capacitor.

16. A microelectronic device comprising:

a plurality of organic dielectric layers; and

a capacitor formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers, and the capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes, wherein the capacitor has a capacitance density of at least 10 nanoFarad per millimeter 2 .

17. A microelectronic device comprising:

a plurality of organic dielectric layers; and

a capacitor formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers, and the capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes, wherein the capacitor further comprises a first seed layer that is disposed on the first conductive electrode and the ultra-high-k dielectric layer is disposed on the first seed layer, wherein the first seed layer comprises a conductive layer that is different than the first and second conductive electrodes, and wherein the first seed layer comprises a thermal buffer layer.

18. The microelectronic device of claim 17 , wherein the capacitor further comprises a second seed layer that is disposed on the ultra-high-k dielectric layer and the second conductive electrode is disposed on the second seed layer.

19. A microelectronic device comprising:

a plurality of organic dielectric layers; and

a capacitor formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers, and the capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes, wherein each electrode of the capacitor is formed with an interdigitated configuration.