Epitaxial features confined by dielectric fins and spacers

1. A method, comprising:

receiving a substrate;

forming a semiconductor fin extending from the substrate;

forming an isolation structure surrounding the semiconductor fin;

forming first and second dielectric fins above the isolation structure and sandwiching the semiconductor fin, wherein each of the first and second dielectric fins is spaced apart from the semiconductor fin, wherein each of the first and second dielectric fins is partially embedded in the isolation structure, and wherein the isolation structure prevents the first and second dielectric fins from physically contacting the substrate;

depositing a spacer feature filling spaces between the semiconductor fin and the first and second dielectric fins;

performing an etching process to recess the semiconductor fin, resulting in a trench between portions of the spacer feature;

epitaxially growing a semiconductor material in the trench; and

after the epitaxially growing of the semiconductor material, forming a gate stack directly above the semiconductor fin and the first and second dielectric fins.

2. The method of claim 1 , wherein the etching process also recesses the spacer feature.

3. The method of claim 1 , wherein the etching process also laterally etches the spacer feature to result in the trench having a top opening wider than a bottom opening.

4. The method of claim 1 , wherein the etching process also recesses the first and second dielectric fins.

5. The method of claim 1 , wherein the recessed semiconductor fin is below a top surface of the isolation structure.

6. The method of claim 1 , further comprising, before the depositing of the spacer feature:

forming a temporary gate structure over the semiconductor fin and the first and second dielectric fins, wherein the spacer feature is also deposited on sidewalls of the temporary gate structure.

7. The method of claim 1 , further comprising:

forming a source/drain (S/D) contact feature in physical contact with the semiconductor material and one of the first and second dielectric fins.

8. The method of claim 7 , wherein the one of the first and second dielectric fins extends into the S/D contact feature.

9. The method of claim 7 , wherein the one of the first and second dielectric fins is below a bottommost portion of the S/D contact feature.

10. The method of claim 1 , wherein the forming of the isolation structure uses atomic layer deposition (ALD).

11. A method, comprising:

providing a structure having a substrate, a semiconductor fin extending from the substrate, an isolation structure surrounding the semiconductor fin, and a dielectric fin above the isolation structure, wherein the dielectric fin is spaced apart from the semiconductor fin, wherein a bottom portion of the dielectric fin is embedded in the isolation structure, and wherein the isolation structure prevents the dielectric fin from physically contacting the substrate;

depositing a spacer feature on sidewalls of the semiconductor fin and the dielectric fin;

recessing the semiconductor fin, resulting in a trench between portions of the spacer feature;

epitaxially growing a semiconductor material in the trench; and

forming a metal gate stack directly above the semiconductor fin and the dielectric fin.

12. The method of claim 11 , wherein the spacer feature fills a space between the semiconductor fin and the dielectric fin.

13. The method of claim 11 , wherein the dielectric fin and the spacer feature substantially remain during the recessing of the semiconductor fin.

14. The method of claim 11 , wherein the semiconductor fin is recessed to a level at or below a top surface of the isolation structure.

15. The method of claim 11 , wherein the recessing of the semiconductor fin also laterally etches the spacer feature to result in the trench having a top opening wider than a bottom opening.

16. A method, comprising:

providing a structure having a substrate and first and second semiconductor fins above the substrate;

forming a trench between the first and second semiconductor fins by depositing an isolation structure over the substrate and on sidewalls of the first and second semiconductor fins, wherein the trench is between two portions of the isolation structure that are on two opposing sidewalls of the first and second semiconductor fins;

after the depositing of the isolation structure, depositing a dielectric fin in the trench;

recessing the isolation structure to fall below top surfaces of the first and second semiconductor fins and the dielectric fin;

depositing an oxide layer over at least top and sidewall surfaces of the first and second semiconductor fins;

depositing a spacer feature over the oxide layer and filling spaces between the first and second semiconductor fins and the dielectric fin;

recessing the first and second semiconductor fins, resulting in two trenches between portions of the spacer feature;

epitaxially growing one or more semiconductor materials in the two trenches; and

forming a metal gate stack engaging the first and second semiconductor fins and the dielectric fin.

17. The method of claim 16 , wherein the depositing of the isolation structure uses atomic layer deposition (ALD), and the depositing of the oxide layer uses ALD.

18. The method of claim 16 , wherein the recessing of the first and second semiconductor fins also recesses the portions of the spacer feature that form sidewalls of the two trenches.

19. The method of claim 18 , wherein the recessing of the first and second semiconductor fins also recesses the dielectric fin.

20. The method of claim 16 , further comprising, before the depositing of the spacer feature:

forming a temporary gate structure over the oxide layer, wherein the spacer feature is also deposited on sidewalls of the temporary gate structure.