Structure and methodology for detecting defects during MEMS device production
A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure. Methodology entails measuring a capacitance between the detection structure and the substrate, measuring another capacitance between the reference structure and substrate, and comparing the two capacitances to determine whether defects exist.
1. A wafer comprising:
a substrate; and
a process control monitor (PCM) structure formed on the substrate, the PCM structure comprising:
a detection structure including a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement; and
a reference structure including a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material, wherein the insulator material does not overlie the detection structure.
2. The wafer of claim 1 wherein the substrate comprises a substrate oxide layer overlying a silicon layer, and the detection and reference structures are formed on the substrate oxide layer.
3. The wafer of claim 1 wherein the second electrically conductive line arrangement is a duplicate of the first electrically conductive line arrangement.
4. The wafer of claim 1 wherein each of the first and second electrically conductive line arrangements comprises multiple line segments spaced apart by gaps, the line segments having different segment widths.
5. The wafer of claim 1 wherein each of the first and second electrically conductive line arrangements comprises multiple line segments spaced apart by gaps, the gaps having different gap widths.
6. A wafer comprising:
a substrate; and
a process control monitor (PCM) structure formed on the substrate, the PCM structure comprising:
a detection structure including a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement; and
a reference structure including a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material, wherein each of the first and second electrically conductive line arrangements comprises a first comb structure having first line segments and a second comb structure having second line segments that are interdigitated with the first line segments.
7. A wafer comprising:
a substrate;
a process control monitor (PCM) structure formed on the substrate, the PCM structure comprising:
a detection structure including a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement; and
a reference structure including a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material;
a first probe pad electrically coupled with the first electrically conductive line arrangement;
a second probe pad electrically coupled with the substrate, the first and second probe pads being configured for measurement of a first capacitance value between the first electrically conductive line arrangement of the detection structure and the substrate;
a third probe pad electrically coupled with the second electrically conductive line arrangement; and
a fourth probe pad electrically coupled with the substrate, the third and fourth probe pads being configured for measurement of a second capacitance value between the second electrically conductive line arrangement of the reference structure and the substrate.
8. A wafer comprising:
a substrate;
a process control monitor (PCM) structure formed on the substrate, the PCM structure comprising:
a detection structure including a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement; and
a reference structure including a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material; and
a plurality of microelectromechanical systems (MEMS) devices formed in the second structural layer.
9. The wafer of claim 8 wherein the MEMS devices are laterally spaced apart from the detection structure.
10. The wafer of claim 8 wherein at least one of the MEMS devices overlies the detection structure and the insulator material is absent between the detection structure and the at least one of the MEMS devices.
11. The wafer of claim 1 further comprising multiple ones of the PCM structure located at various distinct regions on the wafer.
12. A wafer comprising:
a substrate; and
a process control monitor (PCM) structure formed on the substrate, the PCM structure comprising:
a detection structure including a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement; and
a reference structure including a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material, wherein:
the first structural layer comprises a first polysilicon material layer;
the second structural layer comprises a second polysilicon material layer;
the first and second protection layers comprise a silicon nitride material; and
the insulator material comprises a sacrificial oxide material.