System and method for improved GNSS sensitivity via combining acquisition and track correlation hypotheses

1. An apparatus, comprising:

a memory; and

a processor configured to:

conduct acquisition of K values with N peaks, where K and N are integers;

store the K values in the memory;

select J of the N peaks and include the J peaks in track, where J is an integer less than or equal to N;

combine acquisition non-coherent summations (NCSs) and track NCSs of coherent correlations in a metric; and

form a measurement unless the metric indicates that the measurement should be abandoned.

2. The apparatus of claim 1 , wherein the apparatus is one of a global navigation satellite system (GNSS) including a global positioning system (GPS), Glonass, Galileo, Beidou, and an augmentation system.

3. The apparatus of claim 1 , wherein the N peaks are highest energy peaks.

4. The apparatus of claim 1 , wherein the metric is one of a signal energy check, lock detection, continuous wave (CW) detection, cross correlation detection, multipath detection, frequency side lobe detection, range measurement, and range rate measurement.

5. The apparatus of claim 2 , wherein the GNSS comprises:

an antenna;

a radio frequency/intermediate frequency (RF/IF) device connected to the antenna;

an analog-to-digital converter (ADC) connected to the RF/IF device, including an input for receiving a frequency signal, and an output bus;

a carrier mixer and filter connected to the ADC;

a sample storage memory connected to the carrier mixer and filter;

a local carrier generator;

a carrier mixer connected to the sample storage memory and the local carrier generator;

a local code clock generator, including an input for receiving a code phase signal;

a course/acquisition (C/A) code generator connected to the local code clock generator, including an input for receiving a code select signal, and an output bus;

an array of matched filter/correlators connected to the carrier mixer and the C/A code generator;

a Fast Fourier Transform (FFT) connected to the array of matched filter/correlators;

a square root device connected to the FFT;

an NCS hypothesis summation and storage memory connected to the square root device;

a peak sorter connected to the NCS hypothesis summation and storage memory; and

a microprocessor connected to the peak sorter.

6. The apparatus of claim 1 , wherein the J peaks do not include duplicates or near duplicates.

7. The apparatus of claim 6 , wherein the near duplicate is within ½ chip in code phase and within 10 Hz in carrier frequency.

8. The apparatus of claim 1 , wherein each J peak includes adjacent correlators.

9. The apparatus of claim 8 , wherein the processor is further configured to use the adjacent correlators to estimate peak code phase and carrier frequency from acquisition correlations.

10. A method, comprising:

conducting, by a processor, acquisition of K values with N peaks, where K and N are integers;

storing, in a memory, the K values;

selecting J of the N peaks and including the J peaks in track, where J is an integer less than or equal to N;

combining acquisition non-coherent summations (NCSs) and track NCS of coherent correlations in a metric; and

forming a measurement unless the metric indicates that the measurement should be abandoned.

11. The method of claim 10 , wherein the N peaks are highest energy peaks.

12. The method of claim 10 , wherein the metric is one of a signal energy check, lock detection, continuous wave (CW) detection, cross correlation detection, multipath detection, frequency side lobe detection, range measurement, and range rate measurement.

13. The method of claim 10 , wherein the J peaks do not include duplicates or near duplicates.

14. The method of claim 13 , wherein the near duplicate is within Y2 chip in code phase and within 10 Hz in carrier frequency.

15. The method of claim 10 , wherein each J peak includes adjacent correlators.

16. The method of claim 15 , wherein the adjacent correlators are used to estimate peak code phase and carrier frequency from acquisition correlations.

17. A method of manufacturing an apparatus, comprising:

forming the apparatus on a wafer or a package with at least one other apparatus, wherein the apparatus comprises a memory and a processor configured to conduct acquisition of K values with N peaks, where K and N are integers, store the K values in the memory, select J of the N peaks and include the J peaks in track, where J is an integer less than or equal to N, combine acquisition and track non-coherent summations (NCSs) of coherent correlations in a metric; and form a measurement unless the metric indicates that the measurement should be abandoned; and

testing the apparatus, wherein testing the apparatus comprises testing the apparatus using one or more electrical to optical converters, one or more optical splitters that split an optical signal into two or more optical signals, and one or more optical to electrical converters.

18. The method of claim 17 , wherein the metric is one of a signal energy check, lock detection, continuous wave (CW) detection, cross correlation detection, multipath detection, frequency side lobe detection, range measurement, and range rate measurement.

19. A method of constructing an integrated circuit, comprising:

generating a mask layout for a set of features for a layer of the integrated circuit, wherein the mask layout includes standard cell library macros for one or more circuit features that include an apparatus comprising a memory and a processor configured to conduct acquisition of K values with N peaks, where K and N are integers, store the K values in the memory, select J of the N peaks and include the J peaks in track, where J is an integer less than or equal to N, combine acquisition and track non-coherent summations (NCSs) of coherent correlations in a metric; and form a measurement unless the metric indicates that the measurement should be abandoned;

disregarding relative positions of the macros for compliance to layout design rules during the generation of the mask layout;

checking the relative positions of the macros for compliance to layout design rules after generating the mask layout;

upon detection of noncompliance with the layout design rules by any of the macros, modifying the mask layout by modifying each of the noncompliant macros to comply with the layout design rules;

generating a mask according to the modified mask layout with the set of features for the layer of the integrated circuit; and

manufacturing the integrated circuit layer according to the mask.

20. The method of claim 19 , wherein the metric is one of a signal energy check, lock detection, continuous wave (CW) detection, cross correlation detection, multipath detection, frequency side lobe detection, range measurement, and range rate measurement.