Thin film transistor and manufacturing method thereof, display substrate and manufacturing method thereof, and display device
The present disclosure provides a thin film transistor and a manufacturing method thereof, a display substrate and a manufacturing method thereof, and a display device. The thin film transistor of the embodiments of the present disclosure comprises an active layer pattern disposed on a base substrate, a gate electrode insulating pattern disposed on the active layer pattern, and a gate electrode disposed on the gate electrode insulating pattern, wherein a conductive pattern is disposed between the gate electrode and the gate electrode insulating pattern, the conductive pattern being electrically connected to the gate electrode, and an orthographic projection of the conductive pattern on the base substrate being overlapped with an orthographic projection of the gate electrode insulating pattern on the base substrate.
1. A thin film transistor, comprising:
a base substrate;
an active layer pattern disposed on the base substrate;
a gate electrode insulating pattern disposed on the active layer pattern; and
a gate electrode disposed on the gate electrode insulating pattern; said thin film transistor further comprising:
a conductive pattern disposed between the gate electrode and the gate electrode insulating pattern,
wherein, the conductive pattern is electrically connected to the gate electrode, and an orthographic projection of the conductive pattern on the base substrate is completely overlapped with an orthographic projection of the gate electrode insulating pattern on the base substrate, and
wherein an orthographic projection of the gate electrode on a base substrate is not completely overlapped with the orthographic projection of the conductive pattern on the base substrate.
2. The thin film transistor according to claim 1 , wherein the conductive pattern comprises a non-metallic conductive material.
3. The thin film transistor according to claim 2 , wherein the conductive pattern comprises a graphene material or carbon nanotubes.
4. The thin film transistor according to claim 1 , wherein the thin film transistor further comprises a buffer layer disposed between the base substrate and the active layer pattern.
5. The thin film transistor according to claim 1 , wherein the thin film transistor further comprises an interlayer dielectric layer overlaying the gate electrode, and a source electrode and a drain electrode disposed on the interlayer dielectric layer, wherein the source electrode and the drain electrode are electrically connected to the active layer pattern through via holes respectively.
6. A display substrate comprising the thin film transistor according to claim 1 .
7. The display substrate according to claim 6 , wherein the display substrate further comprises a pixel electrode, wherein the pixel electrode is disposed in the same layer and made from the same material as the conductive pattern; and
the pixel electrode is electrically connected to a drain electrode of the thin film transistor.
8. The display substrate according to claim 7 , wherein the display substrate further comprises a first insulating pattern disposed in the same layer as the gate electrode insulating pattern.
9. The display substrate according to claim 8 , wherein the display substrate further comprises a color film disposed between the first insulating pattern and the pixel electrode.
10. The display substrate according to claim 7 , wherein the display substrate further comprises an etching-blocking and retaining pattern,
wherein the etching-blocking and retaining pattern is disposed in the same layer and made from the same material as the gate electrode.
11. The display substrate according to claim 10 , wherein the display substrate further comprises a passivating layer overlaying the thin film transistor and a pixel definition layer disposed on the passivating layer.
12. A display device comprising the display substrate according to claim 6 .
13. A manufacturing method of a thin film transistor, comprising:
forming an active layer pattern on a base substrate; and
forming a gate electrode insulating pattern, a conductive pattern and a gate electrode, which are sequentially arranged in lamination, on a side of the base substrate on which the active layer pattern is formed,
wherein an orthographic projection of the conductive pattern on the base substrate is completely overlapped with an orthographic projection of the gate electrode insulating pattern on the base substrate, and the gate electrode is disposed on the conductive pattern and is electrically connected to the conductive pattern, and
wherein an orthographic projection of the gate electrode on the base substrate is not completely overlapped with the orthographic projection of the conductive pattern on the base substrate.
14. The manufacturing method according to claim 13 , wherein said forming the gate electrode insulating pattern, the conductive pattern and the gate electrode, which are sequentially arranged in lamination, comprising:
fabricating an insulating film, a first conductive film and a second conductive film sequentially on a side of the base substrate on which the active layer pattern is formed;
etching the second conductive film by a wet etching process to form the gate electrode; and
etching the insulating film and the first conductive film by a dry etching process to form the gate electrode insulating pattern and the conductive pattern.
15. The manufacturing method according to claim 13 , wherein, before forming the active layer pattern, the method further comprises:
forming a buffer layer on the base substrate.
16. The manufacturing method according to claim 13 , wherein, after forming the gate electrode, the method further comprises:
forming an interlayer dielectric layer overlaying the gate electrode; and
forming a source electrode and a drain electrode on the interlayer dielectric layer, the source electrode and the drain electrode being electrically connected to the active layer pattern through via holes respectively.
17. A manufacturing method of a display substrate, comprising:
forming a semiconductor layer on a base substrate, the semiconductor layer comprising an active layer pattern; and
forming an insulating layer, a first conductive layer and a second conductive layer, which are sequentially arranged in lamination, on a side of the base substrate on which the semiconductor layer is formed,
wherein the insulating layer comprises a gate electrode insulating pattern and a first insulating pattern, the first conductive layer comprises a conductive pattern and a pixel electrode, and the second conductive layer comprises a gate electrode and an etching-blocking and retaining pattern, wherein an orthographic projection of the conductive pattern on the base substrate is completely overlapped with an orthographic projection of the gate electrode insulating pattern on the base substrate, and the gate electrode is disposed on the conductive pattern and is electrically connected to the conductive pattern, and wherein an orthographic projection of the gate electrode on the base substrate is not completely overlapped with the orthographic projection of the conductive pattern on the base substrate.
18. The manufacturing method according to claim 17 , wherein, after forming the second conductive layer, the method further comprises:
forming an interlayer dielectric layer overlaying the second conductive layer;
forming a source electrode and a drain electrode on the interlayer dielectric layer;
forming a passivating layer overlaying the source electrode and the drain electrode; and
forming a pixel definition layer on the passivating layer.