Segmented digital-to-analog converter
Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.
1. A circuit comprising:
a decoder having a binary-coded digital input, a first bit output, and a second bit output;
a calibration memory having a first input, a second input, and a calibration code output, the first input of the calibration memory coupled to the first bit output of the decoder, and the second input of the calibration memory coupled to the second bit output of the decoder;
a resistor digital-to-analog converter (DAC) having a first input, a second input, and an output, the first input of the resistor DAV coupled to the first bit output of the decoder; and
a calibration circuit having a first input, a second input, and an output, the first input of the calibration circuit coupled to the output of the calibration memory, and the second input of the calibration circuit coupled to the second bit output of the decoder.
2. The circuit of claim 1 , further comprising an interpolation DAC having a first input and a second input, the first input of the interpolation DAC is coupled to the output of the resistor DAC, and the second input is coupled to the output of the calibration circuit,
wherein the decoder has a an intermediate bit output.
3. The circuit of claim 1 , wherein the resistor DAC is a resistor-two-resistor (R-2R) DAC.
4. The circuit of claim 1 , wherein the decoder has an intermediate significant bit output.
5. The DAC circuit of claim 4 , wherein the calibration memory has a third input and the calibration circuit has a third input, the third input of the calibration memory coupled to the intermediate significant bit output of the decoder, and the third input of the calibration circuit coupled to the intermediate significant bit output of the decoder.
6. The circuit of claim 1 , wherein the resistor DAC further comprises:
a resistive chopper circuit, including a plurality of chopper resistors; and
a chopper switching circuit.
7. The circuit of claim 1 ,
wherein the resistor DAC is a matrix DAC, including the plurality of resistors configured in a matrix of resistors with a plurality of rows and a plurality of columns;
wherein a first set of the plurality of switches of the first switching circuit are configured in the matrix to selectively connect a corresponding one of the tap nodes with a corresponding column line of the matrix based on one of a first set of switching control signals along a corresponding row line of the matrix;
wherein a second set of the plurality of switches of the first switching circuit are configured in the matrix to selectively connect a corresponding one of the row lines to the first converter output based on a corresponding one of a set of second switching control signals;
wherein the resistor DAC further comprises:
a first decoder to provide the first set of switching control signals based on a most significant set of bits of a first subword, and
a second decoder to provide the second set of switching control signals based on a least significant set of bits of the first subword.