IP Library › Granted Patent US 10,947,641
Granted Patent B2
US 10,947,641 · App. 16/497,842 · Granted Mar 16, 2021

Group III nitride semiconductor substrate and method of manufacturing group III nitride semiconductor substrate

Inventors: Hiroki Goto (Tochigi, JP); Yujiro Ishihara (Tochigi, JP)
Assignee: FURUKAWA CO., LTD.
C30B29/406C23C16/0209C23C16/303C30B25/183C30B25/186C30B29/68H01L29/2003
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Quick Facts
Patent No.
US 10,947,641
App. No.
16/497,842
Granted
Mar 16, 2021
Kind
B2
Abstract

There is provided a group III nitride semiconductor substrate (free-standing substrate ( 30 )) that is formed of a group III nitride semiconductor crystal and has a thickness of 300 μm or more and 1000 μm or less. Both exposed first and second main surfaces in a relationship of top and bottom are semipolar planes. A difference in a half width of an X-ray rocking curve (XRC) measured by making X-rays incident on each of the first and second main surfaces in parallel to an m axis of the group III nitride semiconductor crystal is 500 arcsec or less.

Claims (22)

1. A group III nitride semiconductor substrate that is formed of a group III nitride semiconductor crystal and has a thickness of 300 μm or more and 1000 μm or less, wherein both exposed first and second main surfaces in a relationship of top and bottom are semipolar planes, and a difference between a half width of an X-ray rocking curve (XRC) measured by making X-rays incident on the first main surface in parallel to an m axis of the group III nitride semiconductor crystal and a half width of an X-ray rocking curve (XRC) measured by making X-rays incident on the second main surface in parallel to the m axis of the group III nitride semiconductor crystal is 500 arcsec or less.

2. The group III nitride semiconductor substrate according to claim 1 ,

wherein the difference between the half width of the XRC measured by making X-rays incident on the first main surface in parallel to the m axis of the group III nitride semiconductor crystal and the half width of the X-ray rocking curve (XRC) measured by making X-rays incident on the second main surface in parallel to the m axis of the group III nitride semiconductor crystal is 300 arcsec or less.

3. The group III nitride semiconductor substrate according to claim 1 ,

wherein for both the first and second main surfaces, the half width of the XRC measured by making X-rays incident in parallel to the m axis of the group III nitride semiconductor crystal is 500 arcsec or less.

4. The group III nitride semiconductor substrate according to claim 1 ,

wherein the difference between the half width of the XRC measured by making X-rays incident on the first main surface in parallel to a projection axis of a c axis of the group III nitride semiconductor crystal and the half width of the XRC measured by making X-rays incident on the second main surface in parallel to the projection axis of the c axis of the group III nitride semiconductor crystal is 500 arcsec or less.

5. The group III nitride semiconductor substrate according to claim 4 ,

wherein the difference between the half width of the XRC measured by making X-rays incident on the first main surface in parallel to the projection axis of the c axis of the group III nitride semiconductor crystal and the half width of the XRC measured by making X-rays incident on the second main surface in parallel to the projection axis of the c axis of the group III nitride semiconductor crystal is 300 arcsec or less.

6. The group III nitride semiconductor substrate according to claim 4 ,

wherein for both the first and second main surfaces, the half width of the XRC measured by making X-rays incident in parallel to the projection axis of the c axis of the group III nitride semiconductor crystal is 500 arcsec or less.

7. A method of manufacturing the group III nitride semiconductor substrate of claim 1 , comprising:

a substrate preparation step of preparing a sapphire substrate;

a heat treatment step of performing heat treatment on the sapphire substrate after the substrate preparation step;

a pre-flow step of supplying a metal-containing gas onto the sapphire substrate after the heat treatment step;

a buffer layer forming step of forming a buffer layer over the sapphire substrate under growth conditions of a growth temperature of 800° C. or higher and 950° C. or lower and a pressure of 30 torr or higher and 200 torr or lower after the pre-flow step;

a first growth step of forming a first growth layer by growing a group III nitride semiconductor over the buffer layer under growth conditions of a growth temperature of 800° C. or higher and 1025° C. or lower, a pressure of 30 torr or higher and 200 torr or lower, and a growth rate of 10 μm/h or higher using a metal organic chemical vapor deposition (MOCVD) method after the buffer layer forming step; and

a second growth step of forming a second growth layer by growing a group III nitride semiconductor over the first growth layer using an HVPE method after the first growth step.

8. The method of manufacturing a group III nitride semiconductor substrate according to claim 7 , further comprising:

a cutting step of cutting the group III nitride semiconductor substrate from a bulk crystal including the first growth layer and the second growth layer.

9. The method of manufacturing a group III nitride semiconductor substrate according to claim 8 ,

wherein, in the cutting step, the group III nitride semiconductor substrate is cut out from a portion having a growth thickness of 3 mm or more within the bulk crystal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2019
From: GOTO, HIROKI; ISHIHARA, YUJIRO
To: FURUKAWA CO., LTD.
Reel/Frame 050497/0469 →
Priority Claims (1)
JP JP2017-064486 · Mar 29, 2017 · national
Continuity (1)
Related Publication 20200032418A1 · Jan 30, 2020