IP Library › Granted Patent US 10,949,351
Granted Patent B2
US 10,949,351 · App. 16/393,990 · Granted Mar 16, 2021

Bits register for synonyms in a memory system

Inventors: Martin Recktenwald (Schoenaich, DE); Willm Hinrichs (Holzgerlingen, DE)
Assignee: International Business Machines Corporation
G06F12/0828G06F12/0844G06F12/10G06F12/1054G06F12/1063G06F12/0851G06F2212/683
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Quick Facts
Patent No.
US 10,949,351
App. No.
16/393,990
Granted
Mar 16, 2021
Kind
B2
Abstract

In an approach to tracking and invalidating memory address synonyms in a memory system includes establishing a bits register for a first virtual address in a memory system, the bits register having synonym fields representing each bit of a first synonym identifier portion of the first virtual address, the first virtual address being mapped to a physical address; determining, for a second virtual address mapped to the physical address, the second virtual address having a second synonym identifier portion, a set of differing bits within the second synonym identifier portion compared to the first synonym identifier portion; and registering the set of differing bits in the bits register.

Claims (42)

1. A method for managing memory address synonyms, the method comprising:

establishing a bits register for a first virtual address in a memory system, the bits register having synonym fields representing each bit of a first synonym identifier portion of the first virtual address, the first virtual address being mapped to a physical address;

determining, for a second virtual address mapped to the physical address, the second virtual address having a second synonym identifier portion, a set of differing bits within the second synonym identifier portion compared to the first synonym identifier portion; and

registering the set of differing bits in the bits register.

2. The method of claim 1 , further comprising:

receiving a fetch request excluding synonyms from mapping to the physical address; and

generating a set of synonyms within the memory system based on the bits register.

3. The method of claim 2 , further comprising invalidating the set of synonyms within the memory system.

4. The method of claim 2 , wherein generating the set of synonyms comprises generating each binary combination represented by the bits register.

5. The method of claim 1 , further comprising recording the first synonym identifier portion in a first synonym identifier field and the second synonym identifier portion in a second synonym identifier field of a synonym table.

6. The method of claim 5 , wherein the synonym table includes a limited number of synonym identifier fields.

7. The method of claim 6 , further comprising determining that each of the synonym identifier fields of the synonym table contains a respectively corresponding synonym identifier portion.

8. The method of claim 7 , further comprising:

responsive to determining that each of the synonym identifier fields of the synonym table contains a respectively corresponding synonym identifier portion, setting an overflow bit in the synonym table.

9. The method of claim 6 , wherein the selected number of synonym identifier portions stored directly in the synonym table is less than or equal to four.

10. The method of claim 5 , further comprising:

determining a next available synonym identifier field entry in of the synonym table, the next available synonym identifier field not containing a synonym identifier portion; and

recording a third synonym identifier portion associated with a third virtual address mapped to the physical address in the next available synonym identifier field of the synonym table.

11. A computer program product for managing memory address synonyms, the computer program product comprising:

a computer readable storage medium and program instructions stored on the computer readable storage medium, the program instructions comprising:

program instructions to establish a bits register for a first virtual address in a memory system, the bits register having synonym fields representing each bit of a first synonym identifier portion of the first virtual address, the first virtual address being mapped to a physical address;

program instructions to determine, for a second virtual address mapped to the physical address, the second virtual address having a second synonym identifier portion, a set of differing bits within the second synonym identifier portion compared to the first synonym identifier portion; and

program instructions to register the set of differing bits in the bits register.

12. The computer program product of claim 11 , further comprising:

program instructions to receive a fetch request excluding synonyms from mapping to the physical address; and

program instructions to generate a set of synonyms within the memory system based on the bits register.

13. The computer program product of claim 12 , further comprising program instructions to invalidate the set of synonyms within the memory system.

14. The computer program product of claim 12 , wherein program instructions to generate the set of synonyms comprises program instructions to generate each binary combination represented by the bits register.

15. The computer program product of claim 11 , further comprising program instructions to record the first synonym identifier portion in a first synonym identifier field and the second synonym identifier portion in a second synonym identifier field of a synonym table.

16. A computer system comprising:

one or more computer processors;

one or more computer readable storage media;

program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising:

program instructions to establish a bits register for a first virtual address in a memory system, the bits register having synonym fields representing each bit of a first synonym identifier portion of the first virtual address, the first virtual address being mapped to a physical address;

program instructions to determine, for a second virtual address mapped to the physical address, the second virtual address having a second synonym identifier portion, a set of differing bits within the second synonym identifier portion compared to the first synonym identifier portion; and

program instructions to register the set of differing bits in the bits register.

17. The computer system of claim 16 , further comprising:

program instructions to receive a fetch request excluding synonyms from mapping to the physical address; and

program instructions to generate a set of synonyms within the memory system based on the bits register.

18. The computer system of claim 17 , further comprising program instructions to invalidate the set of synonyms within the memory system.

19. The computer system of claim 17 , wherein program instructions to generate the set of synonyms comprises program instructions to generate each binary combination represented by the bits register.

20. The computer system of claim 16 , further comprising program instructions to record the first synonym identifier portion in a first synonym identifier field and the second synonym identifier portion in a second synonym identifier field of a synonym table.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2019
From: RECKTENWALD, MARTIN; HINRICHS, WILLM
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 048989/0321 →
Continuity (2)
Continuation 15711165 · Sep 21, 2017
Related Publication 20190251030A1 · Aug 15, 2019
Cited By (1)
US 12,493,553