Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same
View Patent ↗A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
1. A semiconductor device comprising:
an active pillar extending upward from a top surface of a substrate;
a bit line coupled to the active pillar at a first level and buried within the substrate;
a gate electrode coupled to the active pillar at a second level higher than the first level; and
a capacitor coupled to the active pillar at a third level higher than the second level,
wherein the first level to the third level of the active pillar are doped with impurities having the same conductivity,
wherein a top surface of the bit line and a top surface of a liner insulation layer are substantially level with the top surface of the substrate, and
wherein the bit line is disposed over the liner insulation layer that is disposed along inner sidewalls and a bottom side of a recess within the substrate.
2. The semiconductor device of claim 1 ,
wherein the active pillar is doped at substantially the same concentration throughout the first level and the third level.
3. The semiconductor device of claim 2 ,
wherein the active pillar at the first level forms of a first impurity region,
wherein the active pillar at the second level forms of a second impurity region,
wherein the active pillar at the third level forms of a third impurity region, and
wherein substantially no junction is formed among the first, the second, and the third impurity regions.
4. The semiconductor device of claim 2 ,
wherein a doping concentration in the active pillar throughout the first level to the third level is 8×10 18 to 2×10 19 atom/cm 3 .
5. The semiconductor device of claim 4 ,
wherein a thickness of the active pillar measured from one sidewall to an opposite sidewall is 5˜20 nm.
6. The semiconductor device of claim 4 , further comprising:
a gate insulation layer formed between the active pillar and the gate electrode, and
a thickness of the gate insulation layer is 1˜3 nm.
7. A semiconductor device, comprising:
an active pillar including a first impurity region, a second impurity region provided over the first impurity region, and a third impurity region provided over the second impurity region and extending upward from a top surface of a substrate;
a bit line provided below the first impurity region and coupling the first impurity region;
a gate electrode disposed on a sidewall of the second impurity region; and
a capacitor provided over the third impurity region and coupled to the third impurity region,
wherein the first, the second, and the third impurity regions of the active pillar contain impurities having the same conductivity,
wherein a top surface of the bit line and a top surface of a liner insulation layer are substantially level with the top surface of the substrate, and
wherein the bit line is disposed over the liner insulation layer that is disposed along inner sidewalls and a bottom side of a recess within the substrate.
8. The semiconductor device of claim 7 , wherein the bit line physically contacts the first impurity region.
9. The semiconductor device of claim 7 , wherein the first, the second, and the third impurity regions have substantially the same doping concentration.
10. The semiconductor device of claim 9 , wherein substantially no junction is formed among the first, the second, and the third impurity regions.
11. The semiconductor device of claim 9 , wherein a doping concentration in the first, the second, and the third impurity regions is 8×10 18 to 2×10 19 atom/cm 3 .
12. The semiconductor device of claim 11 , wherein a thickness of the second impurity region measured from one sidewall to an opposite sidewall is 5˜20 nm.
13. The semiconductor device of claim 11 , further comprising:
a gate insulation layer disposed between the active pillar and the gate electrode, the gate insulation layer having a thickness of 1˜3 nm.
14. The semiconductor device of claim 7 , wherein the gate electrode covers one or more sidewalls of the second impurity region.
15. The semiconductor device of claim 7 , wherein the substrate has a nano structure, the nano structure including a nano wire structure, a nano ribbon structure, or both.
16. A semiconductor device, comprising:
a plurality of active pillars arranged in a first direction, each of the active pillars including a first impurity region disposed over a top surface of a substrate and extending in a second direction crossing the first direction, a plurality of second impurity regions disposed over the first impurity region, and a plurality of third impurity regions disposed over the plurality of second impurity regions, respectively, wherein the plurality of second impurity regions is arranged at a constant interval in the second direction;
a gate electrode extending across the plurality of active pillars along the first direction and disposed over sidewalls of corresponding second impurity regions of the plurality of active pillars arranged in the first direction; and
a bit line disposed in the substrate under the first impurity region and being in contact with the first impurity region, the bit line extending in the second direction,
wherein the first, second, and third impurity regions of the active pillar contain impurities of the same conductivity,
wherein a top surface of the bit line and a top surface of the liner insulation layer are substantially level with the top surface of the substrate, and
wherein the bit line is disposed over the liner insulation layer that is disposed along inner sidewalls and a bottom side of a recess within the substrate.
17. The semiconductor device of claim 16 , wherein the first, the second, and the third impurity regions have substantially the same doping concentration, and
wherein a doping concentration in the first, the second, and the third impurity regions is 8×10 18 to 2×10 19 atom/cm 3 .
18. The semiconductor device of claim 17 , wherein a thickness of the second impurity region measured from one sidewall to an opposite sidewall is 5˜20 nm.
19. The semiconductor device of claim 18 , further comprising:
a gate insulation layer disposed between the plurality of active pillars and the gate electrode, the gate insulation layer having a thickness of 1˜3 nm.