Semiconductor memory device and method for manufacturing the same including a plurality of mutually perpendicular trenches having the same depth
A semiconductor device includes a substrate. A method includes the following operations. Multiple first trenches extending in a first direction are formed in the substrate. Multiple second trenches extending in a second direction are formed in the substrate in which the first trenches are formed. The first direction is perpendicular to the second direction. A first depth of a first trench is equal to a second depth of a second trench. A first insulating layer, a conducting layer and a second insulating layer are formed in sequence in the first and second trenches. The conducting layer in the first trench is separated on a cross section in the second direction to form two bit lines connected to sidewalls at either side of the first trench and extending in the first direction. Word lines extending in the second direction are formed on the conducting layer in the first and second trenches.
1. A method for manufacturing a semiconductor device, the semiconductor device comprising a substrate, and the method comprising:
forming multiple first trenches extending in a first direction in the substrate;
forming multiple second trenches extending in a second direction in the substrate with the first trenches formed, wherein the first direction is perpendicular to the second direction, and a first depth of the first trench is equal to a second depth of the second trench;
forming a first insulating layer, a conducting layer and a second insulating layer in sequence in the first trench and the second trench;
separating the conducting layer in the first trench on a cross section in the second direction to form two bit lines connected to sidewalls at either side of the first trench and extending in the first direction; and
forming word lines extending in the second direction on the conducting layer in the first trench and the second trench.
2. The method of claim 1 , wherein the separating the conducting layer in the first trench on a cross section in the second direction comprises:
in the first direction, forming a first gap having a third depth in the first insulating layer, the conducting layer and the second insulating layer in the first trench, wherein the third depth is less than a total thickness of the first insulating layer, the conducting layer and the second insulating layer, and the third depth is greater than a sum of thicknesses of the first insulating layer and the conducting layer; and
filling a first insulating material in the first gap to form a first isolation layer, wherein the conducting layer in the first trench is separated by the first isolation layer on the cross section in the second direction.
3. The method of claim 2 , wherein the first insulating material comprises an oxide.
4. The method of claim 1 , further comprising: after forming the first insulating layer, the conducting layer and the second insulating layer in sequence in the first trench and the second trench,
flattening the second insulating layer and a surface of the substrate to expose a surface of a region of the substrate outside the first trench and the second trench.
5. The method of claim 1 , wherein the forming the word lines extending in the second direction on the conducting layer in the first trench and the second trench comprises:
removing part of the second insulating layer on the conducting layer in the first trench and the second trench to form a depressed region; and
forming the word lines in the depressed region.
6. The method of claim 5 , wherein the forming the word lines in the depressed region comprises:
forming gate oxide layers on sidewalls of the depressed region;
forming a gate conducting layer between the gate oxide layers in the depressed region; and
separating the gate conducting layer in the depressed region into two word lines extending in the second direction on a cross section in the first direction.
7. The method of claim 6 , wherein the forming the gate conducting layer between the gate oxide layers in the depressed region comprises:
depositing a conducting material between the gate oxide layers in the depressed region to form the gate conducting layer, wherein a thickness of the gate conducting layer is less than or equal to a height of the gate oxide layer.
8. The method of claim 6 , wherein the separating the gate conducting layer in the depressed region into two word lines extending in the second direction on the cross section in the first direction comprises:
in the second direction, forming a second gap having a fourth depth in the gate conducting layer, wherein the fourth depth is greater than or equal to a thickness of the gate conducting layer, and the second gap separates the gate conducting layer on the cross section in the first direction; and
filling a second insulating material in the second gap to form a second isolation layer, wherein the gate conducting layer formed by a conducting material at either side of the second isolation layer constitutes the word lines.
9. The method of claim 8 , wherein the second insulating material comprises a nitride.
10. The method of claim 9 , wherein the thickness of the gate conducting layer is less than a height of the gate oxide layer, and the method further comprises: after the separating the gate conducting layer in the depressed region on the cross section in the first direction,
filling a third insulating material between the gate oxide layers in the depressed region to form a third isolation layer, wherein a bottom of the third isolation layer is connected to a top of the second isolation layer and the gate conducting layer.
11. A semiconductor device, comprising:
a substrate;
multiple first trenches extending in a first direction and multiple second trenches extending in a second direction in the substrate; wherein the first direction is perpendicular to the second direction, and a first depth of the first trench is equal to a second depth of the second trench;
a first insulating layer located at bottoms of the first trench and the second trench;
a conducting layer located on the first insulating layer, wherein the conducting layer is separated on a cross section in the second direction, and the conducting layer separated constitutes two bit lines connected to sidewalls at either side of the first trench respectively and extending in the first direction; and
wherein word lines extending in the second direction are provided on the conducting layer in the first trench and the second trench.
12. The semiconductor device of claim 11 , further comprising:
a first isolation layer located on the first insulating layer in the first trench, wherein the conducting layer in the first trench is separated by the first isolation layer on the cross section in the second direction.
13. The semiconductor device of claim 12 , further comprising:
a second insulating layer located between the conducting layer and the word lines, wherein the second insulating layer in the first trench is separated by the first isolation layer on the cross section in the second direction.
14. The semiconductor device of claim 13 , further comprising:
gate oxide layers on part of a sidewall of the first trench and the second trench above the second insulating layer; and
the word lines comprising gate conducting layers corresponding to a semiconductor column located between adjacent gate oxide layers, wherein the gate conducting layers are connected in the second direction.
15. The semiconductor device of claim 14 , further comprising:
a second isolation layer located on the second insulating layer in the second trench, wherein the gate conducting layer in the second trench is separated by the second isolation layer on a cross section in the first direction.