Methods of manufacturing vertical channel semiconductor devices

1. A method of manufacturing a vertical channel semiconductor device, the method comprising:

forming a pillar having a vertical depth on a semiconductor substrate;

forming a gate electrode around a periphery of the pillar;

forming a first source/drain region on the semiconductor substrate below the gate electrode;

etching the first source/drain region to a predetermined depth to expose a sidewall of the first source/drain region;

forming an isotropic space on the sidewall of the first source/drain region vertically spaced apart from an upper surface of the first source/drain region by a predetermined distance;

filling the isotropic space with a conductive layer to form a first source/drain signal line; and

forming a second source/drain region on an exposed upper surface of the pillar.

2. The method of claim 1 , wherein forming the pillar comprises:

forming a pad oxide layer and a hard mask pattern on the semiconductor substrate;

forming the pillar by etching the pad oxide layer and the semiconductor substrate to a predetermined depth in the shape of the hard mask pattern; and

wherein forming the second source/drain region is preceded by:

separating the first source/drain region from adjacent source/drain regions; and

removing the hard mask pattern.

3. The method of claim 2 , wherein forming the pillar comprises:

etching the semiconductor substrate to a first depth using the hard mask pattern as an etch mask;

selectively forming an insulating layer on the sidewall of the etched semiconductor substrate; and

further etching the semiconductor substrate to a second depth using the hard mask pattern and the insulating layer as an etch mask.

4. The method of claim 3 , wherein forming the gate electrode comprises:

isotropically etching the pillar using the hard mask pattern and the insulating layer as an etch mask to form an isotropic space;

forming a gate insulating layer on the surface of the pillar including the isotropic space; and

filling the isotropic space with a conductive layer.

5. The method of claim 2 , wherein forming the gate electrode comprises:

anisotropically etching the pillar to a predetermined width using the hard mask pattern as an etch mask; and

covering the periphery of the pillar with a conductive layer.

6. The method of claim 2 , further comprising forming a gate signal line contacting the gate electrode after forming the first source/drain signal line and before removing the hard mask pattern.

7. The method of claim 6 , wherein forming the gate signal line comprises:

depositing a first interlayer insulating layer on the semiconductor substrate including the first source/drain signal line;

etching a predetermined portion of the first interlayer insulating layer to form a line groove that is perpendicular to the first source/drain signal line and exposes the gate electrode of the sidewall of the pillar;

filling the line groove with an conductive layer contacting the gate electrode;

etching back the conductive layer to a predetermined thickness; and then

filling the line groove with a second interlayer insulating layer.

8. The method of claim 2 , further comprising, after forming the second source/drain region:

depositing a conductive layer on the second interlayer insulating layer to fill a space from which the hard mask pattern is removed;

planarizing the conductive layer to form a contact pad; and

forming a storage electrode on the contact pad.

9. A method of manufacturing a vertical channel semiconductor device, the method comprising:

forming a pad oxide layer and a hard mask pattern on a semiconductor substrate;

forming pillars by etching the pad oxide layer and the semiconductor substrate to a predetermined depth in the shape of the hard mask pattern;

forming a first isotropic space at a position spaced apart from the upper surface of the pillar;

forming a gate insulating layer on the surface of the pillar including the first isotropic space;

filling the first isotropic space of the pillar with a conductive material to form a gate electrode disposed at a position spaced apart from the upper surface of the pillar by a predetermined distance to surround the pillar;

forming a first source/drain region on the semiconductor substrate below the gate electrode;

etching the first source/drain region to a predetermined depth;

forming a second isotropic space on the sidewall of the first source/drain region spaced apart from the upper surface of the first source/drain region by a predetermined distance;

filling the second isotropic space with a conductive layer to form a first source/drain signal line;

separating the first source/drain region;

forming a gate signal line contacting with the gate electrode;

removing the hard mask pattern; and

forming a contact pad contacting with a second source/drain region.

10. The method of claim 9 , wherein the forming of the pillar includes:

etching the semiconductor substrate to a first depth using the hard mask pattern as an etch mask;

selectively forming an insulating layer on the sidewall of the etched semiconductor substrate; and

further etching the semiconductor substrate to a second depth using the hard mask pattern and the insulating layer as an etch mask.

11. The method of claim 9 , wherein the forming of the gate signal line includes:

depositing a first interlayer insulating layer on the resulting structure of the semiconductor substrate on which the first source/drain signal line is formed;

etching a predetermined portion of the first interlayer insulating layer to form a line groove that is perpendicular to the first source/drain signal line and exposes the gate electrode of the pillar;

filling the line groove with an conductive layer contacting with the gate electrode;

etch-backing the conductive layer to a predetermined thickness; and

filling the line groove with a second interlayer insulating layer.

12. The method of claim 11 , wherein the forming of the contact pad includes:

depositing a conductive layer on the second interlayer insulating layer to fill a space from which the hard mask pattern is removed; and

planarizing the conductive layer.

13. The method of claim 9 , further comprising forming a storage electrode on the contact pad after the forming of the contact pad.