Methods of manufacturing vertical channel semiconductor devices

1. A method of manufacturing a vertical channel semiconductor device, the method comprising:

forming a pillar on a semiconductor substrate having a vertical depth and an upper surface displaced from the semiconductor substrate;

forming a space in the pillar at a predetermined position vertically spaced from the upper surface of the pillar;

forming a gate insulating layer on the pillar including the space;

filling the space of the pillar with a conductive material to form a gate electrode around the pillar at a position spaced apart from the upper surface of the pillar by a predetermined distance, wherein the gate electrode entirely surrounds sides of the pillar;

forming a first source/drain region on the semiconductor substrate below the gate electrode; and

forming a second source/drain region on the entire upper surface of the pillar above the gate electrode.

2. The method of claim 1 , wherein forming the pillar comprises:

forming a pad oxide layer and a hard mask pattern on the semiconductor substrate;

forming pillars by etching the pad oxide layer and the semiconductor substrate to a predetermined depth in the shape of the hard mask pattern;

wherein forming the second source/drain region is preceded by removing the hard mask pattern.

3. The method of claim 2 , wherein the forming the pillar includes:

etching the semiconductor substrate to a first depth using the hard mask pattern as an etch mask;

selectively forming an insulating layer on a sidewall of the etched semiconductor substrate; and

further etching the semiconductor substrate to a second depth using the hard mask pattern and the insulating layer as an etch mask.

4. The method of claim 3 , wherein forming the space comprises etching the exposed sidewall of the pillar to a thickness of about 150-500 Å using the hard mask pattern and the insulating layer as an etch mask.

5. The method of claim 2 , wherein forming the gate insulating layer comprises thermally oxidizing a surface of the semiconductor substrate including the pillar.

6. The method of claim 2 , further comprising, between forming the first source/drain region and removing the hard mask pattern:

forming a first source/drain signal line contacting the first source/drain region; and

forming a gate signal line contacting the gate electrode.

7. The method of claim 6 , wherein forming the first source/drain signal line comprises:

etching the first source/drain region to a predetermined depth;

forming an isotropic space in the first source/drain region at a position spaced apart from an upper surface of the first source/drain region by a predetermined distance;

filling a conductive layer in the isotropic space in the first source/drain region; and

etching the semiconductor substrate to a predetermined depth to separate the first source/drain region from an adjacent source drain region associated with another of the pillars.

8. The method of claim 7 , wherein forming the isotropic space in the first source/drain region includes:

forming an insulating spacer to fill a row directional gap between the pillars;

etching the first source/drain region to a selected depth using the insulating spacer as an etch mask;

selectively forming an insulating layer on a sidewall of the exposed first source/drain region;

etching the drain region to a further depth using the insulating spacer as an etch mask; and

isotropically etching the first source/drain region exposed with a portion of the sidewall thereof covered with the insulating layer.

9. The method of claim 6 , wherein forming the first source/drain signal line comprises:

etching the first source/drain region to a predetermined depth;

forming a conductive spacer on a sidewall of the first source/drain region to form the first source/drain signal line; and

etching, using the conductive spacer an etch mask, the semiconductor substrate to separate the first source/drain region from an adjacent source drain region associated with another of the pillars.

10. The method of claim 6 , wherein forming the gate signal line comprises:

depositing a first interlayer insulating layer on the semiconductor substrate including the first source/drain signal line thereon;

etching a portion of the first interlayer insulating layer to form a line groove that is perpendicular to the first source/drain signal line and exposes the gate electrode of the pillar;

filling the line groove with a conductive layer contacting with the gate electrode;

etching back the conductive layer to a predetermined thickness; and then

filling the line groove with a second interlayer insulating layer.

11. The method of claim 10 , further comprising, after forming of the second source/drain region:

depositing a conductive layer on the second interlayer insulating layer to fill a space from which the hard mask pattern is removed; and

planarizing the conductive layer to form a contact pad.

12. The method of claim 11 , further comprising forming a storage electrode on the contact pad.