Apparatus and methods for integrating magnetoresistive devices

1. A method of fabricating an integrated circuit device including a memory portion and a logic portion, comprising:

forming a plurality of magnetoresistive devices spaced apart from each other on the memory portion;

depositing an encapsulant on the plurality of magnetoresistive devices;

depositing a first interlayer dielectric material (ILD) on the plurality of magnetoresistive devices after depositing the encapsulant, wherein the first ILD is a low-k ILD or an ultra low-k ILD;

depositing a second ILD on the first ILD without first planarizing the deposited first ILD;

etching the second ILD and the first ILD to expose top surfaces of the plurality of magnetoresistive devices, wherein the second ILD and the first ILD are etched until a portion of each of the plurality of magnetoresistive devices extends over a top surface of the etched first ILD; and

forming electrical contacts with the exposed top surfaces of the plurality of magnetoresistive devices.

2. The method of claim 1 , further comprising, after depositing the encapsulant, etching the deposited encapsulant such that sidewalls of the plurality of magnetoresistive devices are covered by the encapsulant.

3. The method of claim 1 , further comprising, after depositing the encapsulant, removing the deposited encapsulant from the top surfaces of the plurality of magnetoresistive devices.

4. The method of claim 1 , further comprising exposing the top surfaces of the plurality of magnetoresistive devices after the step of depositing the first ILD.

5. The method of claim 1 , further comprising:

polishing a surface of the deposited second ILD using chemical mechanical polishing (CMP) such that at least a portion of the second ILD is retained over the first ILD after the polishing, wherein the second ILD is not a low-k or an ultra low-k ILD.

6. The method of claim 1 , wherein, during the etching of the second ILD and the first ILD, etchant chemistry is incrementally adjusted to be more selective to the second ILD and then to the first ILD.

7. The method of claim 1 , wherein the first ILD includes at least one of Carbon-doped SiO 2 (SiOC), Carbon-doped Oxide (CDO), Organo Silicate Glass (OSG), and spin-on organics.

8. The method of claim 1 , wherein the second ILD is a conventional ILD including at least one of Tetraethyl Orthosilicate (TEOS) and Silicon Dioxide (SiO 2 ).

9. The method of claim 1 , wherein the second ILD is not a low-k or an ultra low-k ILD.

10. The method of claim 1 , wherein the second ILD is not a low-k or an ultra low-k ILD, and wherein etching the second ILD and the first ILD after depositing the second ILD on the first ILD facilitates planarization of the first ILD without inducing defects therein.

11. The method of claim 1 , further comprising, before forming the electrical contacts, polishing the portion of each of the plurality of magnetoresistive devices extending over the top surface of the etched first ILD.

12. A method of fabricating an integrated circuit device including a memory portion and a logic portion, comprising:

forming a plurality of magnetoresistive devices spaced apart from each other on the memory portion;

depositing an encapsulant on the plurality of magnetoresistive devices;

depositing a first interlayer dielectric material (ILD) on the plurality of magnetoresistive devices after depositing the encapsulant;

depositing a second ILD on the first ILD without first planarizing the deposited first ILD, wherein the second ILD has a higher dielectric constant than the first ILD;

etching the second ILD and the first ILD to expose top surfaces of the plurality of magnetoresistive devices, wherein the second ILD and the first ILD are etched until a portion of each of the plurality of magnetoresistive devices extends over a top surface of the etched first ILD; and

forming electrical contacts with the exposed top surfaces of the plurality of magnetoresistive devices.

13. The method of claim 12 , further comprising polishing a surface of the deposited second ILD using chemical mechanical polishing (CMP) such that at least a portion of the deposited second ILD is retained over the first ILD after the polishing.

14. The method of claim 12 , wherein, during the etching of the second ILD and the first ILD, etchant chemistry is incrementally adjusted to be more selective to the second ILD and then to the first ILD.

15. The method of claim 12 , further comprising, before depositing the first ILD, etching the deposited encapsulant such that at least sidewalls of the plurality of magnetoresistive devices remain covered by the encapsulant.

16. The method of claim 12 , further comprising forming a plurality of metal conductors separated by the second ILD on the logic portion, wherein the second ILD is different from the first ILD.

17. The method of claim 12 , wherein the first ILD is a low-k or an ultra low-k ILD.

18. The method of claim 12 , wherein the second ILD is a conventional ILD including at least one of Tetraethyl Orthosilicate (TEOS) and Silicon Dioxide (SiO 2 ), and wherein etching the second ILD and the first ILD after depositing the second ILD on the first ILD facilitates planarization of the first ILD without inducing defects therein.

19. The method of claim 12 , further comprising, before forming the electrical contacts, polishing the portion of each of the plurality of magnetoresistive devices extending over the top surface of the etched first ILD.

20. The method of claim 12 , further comprising, before forming the electrical contacts, polishing the portion of each of the plurality of magnetoresistive devices extending over the top surface of the etched first ILD using a metal polishing technique.