Memory controller having temperature dependent data program scheme and related method

1. A memory controller ( 120 ), comprising:

an interface ( 140 ), configured to operably communicate with a host device;

a temperature detecting circuit ( 121 ), configured to operably detect an ambient temperature, wherein when the ambient temperature is outside a predetermined temperature range, the temperature detecting circuit ( 121 ) generates a control signal (Sc); and

a processing circuit ( 122 ), coupled to the interface ( 140 ) and the temperature detecting circuit ( 121 ), the processing circuit configured to:

select one of a plurality of data program schemes to program data into a first storage block of a flash memory ( 130 ) according to the control signal (Sc); and

select one of the plurality of data program schemes to program data into a second storage block of the flash memory ( 130 ) according to the control signal (Sc), when the ambient temperature is outside the predetermined temperature range;

wherein a first storage unit of the first storage block is a first bit number, a second storage unit of the second storage block is a second bit number, and the first bit number is greater than the second bit number;

wherein the first storage unit is a form of a quad-level cell (QLC), and the second storage unit is a form of one of a single-level cell (SLC), a multi-level cell (MLC), and a triple-level cell (TLC);

wherein when the ambient temperature falls within a first temperature interval outside the predetermined temperature range, the processing circuit ( 122 ) selects a first data program scheme from the plurality of data program schemes to program the data into the second storage block; when the ambient temperature falls within a second temperature interval outside the predetermined temperature range, the processing circuit ( 122 ) selects a second data program scheme from the plurality of data program schemes to program the data into the second storage block; wherein the second temperature interval is different from the first temperature interval, the first data program scheme and the second data program scheme are different.

2. The memory controller ( 120 ) of claim 1 , wherein the first data program scheme and the second data program scheme are different, the first data program scheme is a 3-bit data program scheme or a 2-bit data program scheme, the second data program scheme is the 2-bit data program scheme or a 1-bit data program scheme.

3. The memory controller ( 120 ) of claim 1 , further comprising:

a power management circuit ( 110 ), coupled to the temperature detecting circuit ( 121 ) and the processing circuit ( 122 ), for providing a first supply power (P 3 ) and a second supply power (P 4 ) to the temperature detecting circuit ( 121 ) and the processing circuit ( 122 ) respectively.

4. The memory controller ( 120 ) of claim 1 , wherein the temperature detecting circuit ( 121 ) comprises:

a temperature detecting unit ( 123 ), configured to operably detect the ambient temperature of the flash memory controller; and

a controlling unit ( 124 ), coupled to the temperature detecting unit ( 123 ), for determining if the ambient temperature is outside the predetermined temperature range, and the controlling unit ( 124 ) generates the control signal (Sc) to the processing circuit ( 122 ) when the ambient temperature is outside the predetermined temperature range.

5. The memory controller ( 120 ) of claim 1 , wherein when the ambient temperature is outside the predetermined temperature range, the processing circuit ( 122 ) is further arranged to reprogram the data stored in the first storage block of the flash memory ( 130 ) into the second storage block of the flash memory ( 130 ) according to the control signal (Sc), wherein a first storage unit of the first storage block is a first bit number, a second storage unit of the second storage block is a second bit number, and the first bit number is larger than the second bit number.

6. The memory controller ( 120 ) of claim 5 , wherein the second storage unit is a form of one of a single-level cell, a multi-level cell, and a triple-level cell, and the first storage unit is a form of a quad-level cell.

7. A method of controlling a flash memory, comprising:

detecting an ambient temperature of the flash memory;

generating a control signal (Sc) when the ambient temperature is outside a predetermined temperature range;

selecting one of a plurality of data program schemes to program data into a first storage block of the flash memory ( 130 ) according to the control signal (Sc); and

selecting one of the plurality of data program schemes to program data into a second storage block of the flash memory ( 130 ) according to the control signal (Sc), when the ambient temperature is outside the predetermined temperature range;

wherein a first storage unit of the first storage block is a first bit number, a second storage unit of the second storage block is a second bit number, and the first bit number is greater than the second bit number;

wherein the first storage unit is a form of a quad-level cell, and the second storage unit is a form of one of a single-level cell, a multi-level cell, and a triple-level cell;

wherein the step of selecting one of the plurality of data program schemes to program the data into the second storage block of the flash memory ( 130 ) according to the control signal (Sc) comprises:

selecting a first data program scheme from the plurality of data program schemes to program the data into the second storage block when the ambient temperature falls within a first temperature interval outside the predetermined temperature range;

and

selecting a second data program scheme from the plurality of data program schemes to program the data into the second storage block when the ambient temperature falls within a second temperature interval outside the predetermined temperature range;

wherein the second temperature interval is different from the first temperature interval;

wherein the first data program scheme and the second data program scheme are different, the first data program scheme is a 3-bit data program scheme or a 2-bit data program scheme, the second data program scheme is the 2-bit data program scheme or a 1-bit data program scheme.

8. The method of claim 7 , wherein the first data program scheme and the second data program scheme are different, the first data program scheme is a 3-bit data program scheme or a 2-bit data program scheme, the second data program scheme is the 2-bit data program scheme or a 1-bit data program scheme.

9. The method of claim 7 , further comprising:

reprograming the data stored in a first storage block of the flash memory ( 130 ) into the second storage block of the flash memory ( 130 ) according to the control signal (Sc), wherein a first storage unit of the first storage block is a first bit number, a second storage unit of the second storage block is a second bit number, and the first bit number is larger than the second bit number.

10. The method of claim 9 , wherein the second storage unit is a form of one of a single-level cell, a multi-level cell, and a triple-level cell, and the first storage unit is a form of a quad-level cell.