IP Library › Granted Patent US 10,957,267

Granted Patent B2

US 10,957,267 · App. 16/711,621 · Granted Mar 23, 2021

Semiconductor device

Inventors: Hajime Kimura (Kanagawa, JP); Atsushi Umezaki (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G09G3/3648 G09G3/2096 G09G3/3677 G09G3/3688 G09G2300/0426 G09G2300/0814 G09G2300/0819 G09G2320/0209 G09G2320/0223 G09G2320/043

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 10,957,267
App. No.: 16/711,621
Granted: Mar 23, 2021
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

Claims (132)

1. A display device comprising:

a first gate driver circuit;

a second gate driver circuit;

a pixel portion between the first gate driver circuit and the second gate driver circuit; and

a gate line,

wherein the first gate driver circuit comprises first to ninth transistors,

wherein the second gate driver circuit comprises tenth to eighteenth transistors,

wherein one of a source and a drain of the first transistor is electrically connected to the gate line,

wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the gate line,

wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the second transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a third wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the second transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring,

wherein a gate of the fourth transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the third transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,

wherein a gate of the fifth transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the third transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the second wiring,

wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the seventh transistor is electrically connected to a fourth wiring,

wherein a gate of the seventh transistor is electrically connected to the fourth wiring,

wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the second wiring,

wherein a gate of the eighth transistor is electrically connected to a fifth wiring,

wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the second wiring,

wherein a gate of the ninth transistor is electrically connected to the gate of the second transistor,

wherein one of a source and a drain of the tenth transistor is electrically connected to the gate line,

wherein the other of the source and the drain of the tenth transistor is electrically connected to a sixth wiring,

wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate line,

wherein the other of the source and the drain of the eleventh transistor is electrically connected to a seventh wiring,

wherein one of a source and a drain of the twelfth transistor is electrically connected to a gate of the eleventh transistor,

wherein the other of the source and the drain of the twelfth transistor is electrically connected to an eighth wiring,

wherein one of a source and a drain of the thirteenth transistor is electrically connected to the gate of the eleventh transistor,

wherein the other of the source and the drain of the thirteenth transistor is electrically connected to the seventh wiring,

wherein a gate of the thirteenth transistor is electrically connected to a gate of the tenth transistor,

wherein one of a source and a drain of the fourteenth transistor is electrically connected to a gate of the twelfth transistor,

wherein the other of the source and the drain of the fourteenth transistor is electrically connected to the eighth wiring,

wherein a gate of the fourteenth transistor is electrically connected to the eighth wiring,

wherein one of a source and a drain of the fifteenth transistor is electrically connected to the gate of the twelfth transistor,

wherein the other of the source and the drain of the fifteenth transistor is electrically connected to the seventh wiring,

wherein a gate of the fifteenth transistor is electrically connected to the gate of the tenth transistor,

wherein one of a source and a drain of the sixteenth transistor is electrically connected to the gate of the tenth transistor,

wherein the other of the source and the drain of the sixteenth transistor is electrically connected to a ninth wiring,

wherein a gate of the sixteenth transistor is electrically connected to the ninth wiring,

wherein one of a source and a drain of the seventeenth transistor is electrically connected to the gate of the tenth transistor,

wherein the other of the source and the drain of the seventeenth transistor is electrically connected to the seventh wiring,

wherein a gate of the seventeenth transistor is electrically connected to a tenth wiring,

wherein one of a source and a drain of the eighteenth transistor is electrically connected to the gate of the tenth transistor,

wherein the other of the source and the drain of the eighteenth transistor is electrically connected to the seventh wiring, and

wherein a gate of the eighteenth transistor is electrically connected to the gate of the eleventh transistor.

2. The display device according to claim 1 , wherein the first wiring is electrically connected to the sixth wiring.

3. The display device according to claim 2 , wherein the second wiring is electrically connected to the seventh wiring.

4. The display device according to claim 3 , wherein at least one of a channel width of the first transistor and a channel width of the second transistor is larger than any one of channel widths of the first to ninth transistors.

5. The display device according to claim 4 , wherein at least one of a channel width of the tenth transistor and a channel width of the eleventh transistor is larger than any one of channel widths of the twelfth to eighteenth transistors.

6. The display device according to claim 1 , wherein the second wiring is electrically connected to the seventh wiring.

7. The display device according to claim 6 , wherein at least one of a channel width of the first transistor and a channel width of the second transistor is larger than any one of channel widths of the first to ninth transistors.

8. The display device according to claim 7 , wherein at least one of a channel width of the tenth transistor and a channel width of the eleventh transistor is larger than any one of channel widths of the twelfth to eighteenth transistors.

9. The display device according to claim 1 , wherein at least one of a channel width of the first transistor and a channel width of the second transistor is larger than any one of channel widths of the first to ninth transistors.

10. The display device according to claim 9 , wherein at least one of a channel width of the tenth transistor and a channel width of the eleventh transistor is larger than any one of channel widths of the twelfth to eighteenth transistors.

11. The display device according to claim 1 , wherein at least one of a channel width of the tenth transistor and a channel width of the eleventh transistor is larger than any one of channel widths of the twelfth to eighteenth transistors.

12. A display device comprising: