High-mobility field effect transistors with wide bandgap fin cladding
Monolithic FETs including a fin of a first III-V semiconductor material offering high carrier mobility is clad with a second III-V semiconductor material having a wider bandgap. The wider bandgap cladding may advantageously reduce band-to-band tunneling (BTBT) leakage current while transistor is in an off-state while the lower bandgap core material may advantageously provide high current conduction while transistor is in an on-state. In some embodiments, a InGaAs cladding material richer in Ga is grown over an InGaAs core material richer in In. In some embodiments, the semiconductor cladding is a few nanometers thick layer epitaxially grown on surfaces of the semiconductor core. The cladded fin may be further integrated into a gate-last finFET fabrication process. Other embodiments may be described and/or claimed.
1. A transistor, comprising:
a fin comprising a core and a cladding on the core, the core comprising a first III-V semiconductor material, and the cladding comprising a second III-V semiconductor material having a wider bandgap than the first III-V semiconductor material;
a gate stack disposed over the cladding within a channel region of the fin; and
source/drain regions disposed over the cladding on opposite sides of the gate stack.
2. The transistor of claim 1 , wherein the core is an In x Ga 1-x As alloy with x being at least 0.6.
3. The transistor of any one of claim 1 , wherein:
the core and cladding are both In x Ga 1-x As alloys; and at least one of:
x for the core is at least 0.6;
x for the cladding is no more than 0.55.
4. The transistor of claim 3 , wherein:
x for the cladding is between 0.30 and 0.55; and
x for the core is between 0.60 and 0.90.
5. The transistor of claim 1 , wherein:
the cladding has a different non-zero thickness within a channel region than within a source/drain region of the fin.
6. The transistor of claim 1 , wherein the fin is disposed on a sub-fin comprising a third III-V semiconductor material having a wider bandgap than the core and the cladding.
7. The transistor of claim 6 , wherein:
the sub-fin is disposed on monocrystalline silicon;
the semiconductor channel region and source/drain regions are monocrystalline;
the gate stack comprises a high-k gate insulator disposed directly on the cladding; and
a metal gate electrode is disposed directly on the high-k gate insulator.
8. The transistor of claim 7 , wherein:
the sub-fin is GaAs;
the core and cladding are both In x Ga 1-x As alloys;
x for the cladding is between 0.30 and 0.55;
x for the core is between 0.60 and 0.90;
the core has a transverse width of 2-5 nm; and
the cladding has a thickness of 1.5-3 nm.
9. The transistor of claim 8 , wherein the transverse width of the sub-fin is equal to that of the core.
10. The transistor of claim 8 , wherein the transverse width of the core is less than that of the sub-fin.
11. The transistor of claim 9 , wherein the impurity-doped source/drain regions comprise a III-V semiconductor material graded from the composition of the cladding to an alloy composition having a bandgap narrower than that of the cladding and the core.
12. A CMOS integrated circuit (IC), comprising:
a substrate comprising silicon;
an n-type fin field effect transistor (finFET) disposed over a first region of the substrate, the n-type finFET further including:
a fin core comprising a ternary III-V semiconductor material having a first alloy composition;
a fin cladding comprising a ternary III-V semiconductor material having a second alloy composition with a wider bandgap than that of the fin core;
a gate stack disposed over the fin cladding within a channel region; and
n-type semiconductor source/drain regions disposed over the fin cladding on opposite sides of the gate stack; and
a p-type finFET disposed over a second region of the substrate, the p-type fin FET comprising a silicon fin.
13. The CMOS IC of claim 12 , wherein:
the fin core is disposed on a sub-fin comprising a III-V semiconductor having a wider bandgap than the fin core and the fin cladding;
the fin core and the fin cladding are both In x Ga 1-x As alloys;
x for the fin cladding is between 0.30 and 0.55;
x for the fin core is between 0.60 and 0.90;
the fin core has a transverse width of 2-5 nm; and
the fin cladding has a thickness of 1.5-3 nm.
14. A mobile computer platform, comprising:
a battery;
a memory; and
a processor coupled to the battery and memory, wherein the processor includes the CMOS IC of claim 12 .
15. A method of fabricating a III-V fin field effect transistor (FET), the method comprising:
forming a fin core disposed on a substrate, the fin core comprising a first III-V semiconductor material having a first alloy composition;
epitaxially growing a fin cladding on at least a sidewall of the fin core, the fin cladding comprising a second III-V semiconductor material having a second alloy composition with a wider bandgap than that of the fin core;
forming a mask over a channel region of the fin cladding; and
epitaxially growing III-V source/drain semiconductor on surfaces of the fin cladding not covered by the mask.
16. The method of claim 15 , wherein:
epitaxially growing the fin core further comprises growing a first In x Ga 1-x As alloy, where x is at least 0.6; and
epitaxially growing the fin cladding further comprises growing a second In x Ga 1-x As alloy, where x is no more than 0.55.
17. The method of claim 15 , wherein forming the fin core further comprises:
forming a trench in a trench layer, the trench exposing a surface of the substrate; epitaxially growing a sub-fin within the trench, the sub-fin comprising a III-V semiconductor having a third alloy composition associated with a wider bandgap than the second alloy composition; and
epitaxially growing the fin core on a surface of the sub-fin III-V semiconductor.
18. The method of claim 17 , wherein:
epitaxially growing the fin core on a surface of the sub-fin III-V semiconductor further comprises growing the fin core within an upper portion of the trench; and
the method further comprises recessing the trench layer to expose the fin core sidewall.
19. The method of claim 17 , wherein the method further comprises wet etching the fin core prior to growing the cladding.
20. The method of claim 17 , wherein:
the first alloy composition comprises In x Ga 1-x As, and x is 0.60 to 0.7;
the second alloy composition comprises In x Ga 1-x As, and x is 0.3 to 0.55;
the third alloy composition comprises Ga and As; and
the cladding is grown to a thickness of 1.5-3 nm.