Series connected stacked vertical transistors for high voltage applications
A method of forming an electrical device that includes forming a multilayered fin composed of a first source/drain layer for a first transistor, a first channel layer for the first transistor, a common source/drain layer for the first transistor and a second transistor, a second channel layer for the second transistor and a second source/drain layer for the second transistor. A common spacer is formed on the common source/drain layer that separates a first opening to the first channel layer from a second opening to the second channel layer. Gate structures are then formed in the first and second openings.
1. A method of forming an electrical device comprising:
forming a multilayered fin composed of a first source/drain layer for a first transistor, a first channel layer for the first transistor, a common source/drain layer for the first transistor and a second transistor, a second channel layer for the second transistor and a second source/drain layer for the second transistor;
forming a common spacer on the common source/drain layer that separates a first opening to the first channel layer from a second opening to the second channel layer; and
forming gate structures in the first and second openings.
2. The method of claim 1 , wherein the gate structures are formed using a replacement gate process.
3. The method of claim 2 , wherein forming the gate structures in the first and second openings comprises forming sacrificial gate structures that includes forming a first sacrificial gate structure that is formed before the common spacer, and forming a second sacrificial gate structure after forming the common spacer.
4. The method of claim 3 , wherein during the replacement gate process the first and second sacrificial gate structures are replaced with functional gate structures, each of the functional gate structures having at least one gate dielectric and at least one gate electrode.
5. The method of claim 1 , wherein the gate structures are formed using a gate first process.
6. The method of claim 1 , wherein the first transistor is a first vertical field effect transistor (VFET), and the second transistor is a second vertical field effect transistor (VFET).
7. The method of claim 6 , wherein the common spacer includes a multi-layered structure of a semiconductor material layer between dielectric layers.
8. The method of claim 7 , further comprising forming a metal semiconductor alloy on the common source/drain layer.
9. The method of claim 8 , wherein forming the meal semiconductor alloy comprises:
removing the semiconductor material layer of the common spacer to expose a sidewall of the common source/drain layer;
forming a metal layer on the sidewall of the common source/drain layer; and
annealing to intermix metal elements from the metal layer and semiconductor elements from the common source/drain layer to form the metal semiconductor alloy.