Delay based comparator
A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.
1. A delay circuit having inputs for a clock signal, a positive input signal, a negative input signal, a positive reference signal and a negative reference signal, the positive input signal and the negative input signal are differential signals and the positive reference signal and the negative reference signal are differential signals, the delay circuit comprising:
a first inverter coupled to a first transistor and a second transistor, the first inverter has a first intermediate delayed clock signal input and a positive delayed clock signal output;
a second inverter coupled to a third transistor and a fourth transistor, the second inverter has a second intermediate delayed clock signal input and a negative delayed clock signal output;
the first transistor has a resistance and is connected to the positive input signal, the positive input signal effects the resistance of the first transistor;
the second transistor has a resistance and is connected to the negative reference signal, the negative reference signal effects the resistance of the second transistor;
the third transistor has a resistance and is connected to the negative input signal, the negative input signal effects the resistance of the third transistor;
the fourth transistor has a resistance and is connected to the positive reference signal, the positive reference signal effects the resistance of the fourth transistor; and
a pair of cross-coupled capacitors coupled to the first and second inverters.
2. The delay circuit of claim 1 , wherein:
the drain of the first transistor is connected to the drain of the second transistor;
the drain of the third transistor is connected to the drain of the fourth transistor;
the resistance of the first transistor in parallel with the second transistor determines a delay in the positive delayed clock signal; and
the resistance of the third transistor in parallel with the fourth transistor determines a delay in the negative delayed clock signal.
3. The delay circuit of claim 2 , comprising:
a fifth transistor connected to a voltage source and an input of the first invertor and having a gate connected to the clock signal, wherein the fifth transistor connects the input of the first inverter to the voltage source when the clock signal is high; and
a sixth transistor connected to the voltage source and an input of the second invertor and having a gate connected to the clock signal, wherein the sixth transistor connects the input of the second inverter to the voltage source when the clock signal is high.
4. A delay circuit for delaying a clock input signal by a delay value, the delay circuit comprising:
a complementary analog voltage input having a positive analog voltage input and a negative analog voltage input;
a complementary reference voltage input having a positive reference voltage input and a negative reference voltage input;
a delayed clock output; and
wherein the delay value is determined based on a difference between the complementary analog voltage input and the complementary reference voltage input.
5. The delay circuit of claim 4 , wherein the delay value is greater for greater differences between the analog voltage input and the reference voltage input.
6. The delay circuit of claim 4 , further comprising:
a first transistor having a first terminal coupled to ground, a control terminal coupled to the clock input signal and a second terminal;
a second transistor having a first terminal coupled to ground, a control terminal coupled to the clock input signal and a second terminal;
a third transistor having a first terminal coupled to the second terminal of the second transistor, a control terminal coupled to the positive analog voltage input and a second terminal;
a fourth transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal coupled to the negative reference voltage input and a second terminal coupled to the second terminal of the third transistor;
a fifth transistor having a first terminal coupled to the first terminal of the fourth transistor, a control terminal coupled to the negative analog voltage input and a second terminal;
a sixth transistor having a first terminal coupled to the first terminal of the third transistor, a control terminal coupled to the positive reference voltage input and a second terminal coupled to the second terminal of the fifth transistor; and
wherein a positive delayed clock output is coupled to the second terminal of the third and fourth transistors and a negative delayed clock output is coupled to the second terminal of the fifth and sixth transistors.
7. The delay circuit of claim 6 , wherein the negative delayed clock output is delayed more than the positive delayed clock output if the analog voltage input is greater than the reference voltage input, and the positive delayed clock output is delayed more than the negative delayed clock output if the analog voltage input is less than the reference voltage input.