System, apparatus and method for loose lock-step redundancy power management in a processor
A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
1. A processor comprising:
a first core;
a second core, wherein the first core and the second core are to execute a task redundantly;
a configuration circuit having a first indicator with a first value to indicate that the first core and the second core are to redundantly execute the task; and
a clock and power controller to cause the first core and the second core to operate at a common frequency to redundantly execute the task based at least in part on the first value of the first indicator, and to cause the first core and the second core to operate at independent frequencies based at least in part on a second value of the first indicator.
2. The processor of claim 1 , wherein the configuration circuit comprises a storage.
3. The processor of claim 2 , wherein the storage comprises a configuration register.
4. The processor of claim 3 , wherein the configuration register is to store the first indicator comprising one or more configuration bits.
5. The processor of claim 1 , wherein the clock and power controller is to dynamically control the first core and the second core to operate at the common frequency to redundantly execute the task.
6. The processor of claim 1 , wherein one of the first core and the second core is to complete the redundant execution of the task prior to the other of the first core and the second core, and within a predetermined time duration.
7. The processor of claim 1 , further comprising a redundancy circuit to compare a first result of the redundant execution of the task on the first core to a second result of the redundant execution of the task on the second core, and raise an error if the first result does not at least substantially match the second result.
8. The processor of claim 7 , wherein the redundancy circuit is to enable the first result to be committed in response to the first result matching the second result.
9. A processor comprising:
a first core;
a second core, wherein the first core and the second core are to execute a task redundantly, wherein the second core is to redundantly execute the task within 1 to 10,000 execution cycles of execution of the task by the first core;
a configuration circuit having a first indicator with a first value to indicate that the first core and the second core are to redundantly execute the task; and
a clock and power controller to cause the first core and the second core to operate at a common frequency to redundantly execute the task based at least in part on the first value of the first indicator, and to cause the first core and the second core to operate at independent frequencies based at least in part on a second value of the first indicator.
10. The processor of claim 9 , wherein the configuration circuit comprises a storage.
11. The processor of claim 10 , wherein the storage comprises a configuration register to store the first indicator comprising one or more configuration bits.
12. The processor of claim 9 , wherein the clock and power controller is to dynamically control the first core and the second core to operate at the common frequency to redundantly execute the task.
13. The processor of claim 9 , further comprising a redundancy circuit to compare a first result of the redundant execution of the task on the first core to a second result of the redundant execution of the task on the second core.
14. The processor of claim 13 , wherein the redundancy circuit is to raise an error if the first result does not at least substantially match the second result.
15. An apparatus comprising:
a first core;
a second core;
a configuration storage to store a first indicator, wherein the first indicator is to indicate that the first core and the second core are to redundantly execute a task when the first indicator has a first value; and
a clock and power controller coupled to the configuration storage, the first core and the second core, wherein the clock and power controller is to cause the first core and the second core to be switched between redundancy in lockstep operation and independent core operation,
wherein in the redundancy in lockstep operation the first core and the second core are to operate at a common frequency to redundantly execute the task based at least in part on the first value of the first indicator, and
wherein in the independent core operation the first core and the second core are to operate at independent frequencies based at least in part on a second value of the first indicator.
16. The apparatus of claim 15 , wherein the configuration circuit comprises a storage.
17. The apparatus of claim 16 , wherein the storage comprises a configuration register to store the first indicator comprising one or more configuration bits.
18. The apparatus of claim 15 , wherein the clock and power controller is to dynamically control the first core and the second core to operate at the common frequency to redundantly execute the task.
19. The apparatus of claim 15 , wherein one of the first core and the second core is to complete the redundant execution of the task prior to the other of the first core and the second core, and within a predetermined time duration.
20. The apparatus of claim 15 , further comprising a redundancy circuit to compare a first result of the redundant execution of the task on the first core to a second result of the redundant execution of the task on the second core, and raise an error if the first result does not at least substantially match the second result.