MRAM device comprising random access memory (RAM) and embedded read only memory (ROM)
One illustrative MRAM device disclosed herein includes a first bit cell and a second bit cell. The first bit cell comprises a first access transistor and a first MTJ stack. The first MTJ stack comprises a first pinned layer and a first free layer, wherein the first pinned layer is connected to the first access transistor. The second bit cell comprises a second access transistor and a second MTJ stack. The second MTJ stack comprises a second pinned layer and a second free layer, wherein the second free layer is connected to the second access transistor.
1. An MRAM array, comprising:
a first bit cell, the first bit cell comprising:
a first access transistor; and
a first MTJ stack, the first MTJ stack comprising a first pinned layer and a first free layer, wherein the first pinned layer is connected to the first access transistor; and
a second bit cell, the second bit cell comprising:
a second access transistor; and
a second MTJ stack, the second MTJ stack comprising a second pinned layer and a second free layer, wherein the second free layer is connected to the second access transistor,
wherein the first bit cell and the second bit cell are positioned in a first row of the MRAM array, and wherein the MRAM array further includes:
first and second source lines;
first and second bit lines; and
a first word line,
wherein the first free layer in the first bit cell is connected to the first bit line, the second pinned layer in the second bit cell is connected to the second bit line, the first access transistor in the first bit cell is connected to the first source line, the second access transistor in the second bit cell is connected to the second source line, a gate of the first access transistor is connected to the first word line and a gate of the second access transistor is connected to the first word line.
2. The MRAM array of claim 1 , wherein the first access transistor is an NFET transistor and the second access transistor is an NFET transistor.
3. An MRAM array, comprising:
a first bit cell, the first bit cell comprising:
a first access transistor; and
a first memory element, wherein the first memory element is arranged in a first orientation relative to the first access transistor; and
a second bit cell, the second bit cell comprising:
a second access transistor; and
a second memory element, wherein the second memory element is arranged in a second orientation relative to the second access transistor, wherein the second orientation is opposite to the first orientation,
wherein each of the first and second memory elements includes a respective first connection point and a respective second connection point, wherein the first connection point of the first memory element is connected to the first access transistor and wherein the second connection point of the second memory element is connected to the second access transistor,
wherein the first bit cell and the second bit cell are positioned in a first row of the MRAM array, and wherein the MRAM array further comprises:
first and second source lines;
first and second bit lines; and
a first word line, wherein the second connection point of the first memory element in the first bit cell is connected to the first bit line, the first connection point in the second memory element in the second bit cell is connected to the second bit line, the first access transistor in the first bit cell is connected to the first source line, the second access transistor in the second bit cell is connected to the second source line, a gate of the first access transistor is connected to the first word line and a gate of the second access transistor is connected to the first word line.
4. The MRAM array of claim 3 , wherein the first access transistor is an NFET transistor and the second access transistor is an NFET transistor.
5. The MRAM array of claim 3 , wherein the first memory element is a first MTJ stack and the second memory element is a second MTJ stack, each of the first MTJ stack and the second MTJ stack including a respective pinned layer and a respective free layer.
6. The MRAM array of claim 5 , wherein the second connection point of the first memory element is the free layer of the first MTJ stack, and the first connection point of the second memory element is the pinned layer of the second MTJ stack.
7. An MRAM array, comprising:
a first bit cell, the first bit cell comprising:
a first access transistor; and
a first memory element, wherein the first memory element is arranged in a first orientation relative to the first access transistor; and
a second bit cell, the second bit cell comprising:
a second access transistor; and
a second memory element, wherein the second memory element is arranged in a second orientation relative to the second access transistor, wherein the second orientation is opposite to the first orientation,
wherein each of the first and second memory elements includes a respective first connection point and a respective second connection point, wherein the first connection point of the first memory element is connected to the first access transistor and wherein the second connection point of the second memory element is connected to the second access transistor,
wherein the first bit cell and the second bit cell are positioned in a first column of the MRAM array, and wherein the MRAM array further comprises:
a first source line;
a first bit line; and
first and second word lines, wherein the second connection point of the first memory element in the first bit cell is connected to the first bit line, the first connection point of the second memory element in the second bit cell is connected to the first bit line, the first access transistor in the first bit cell is connected to the first source line, the second access transistor in the second bit cell is connected to the first source line, a gate of the first access transistor is connected to the first word line and a gate of the second access transistor is connected to the second word line.
8. The MRAM array of claim 7 , wherein the first access transistor is an NFET transistor and the second access transistor is an NFET transistor.
9. The MRAM array of claim 7 , wherein the first memory element is a first MTJ stack and the second memory element is a second MTJ stack, each of the first MTJ stack and the second MTJ stack including a respective pinned layer and a respective free layer.
10. The MRAM array of claim 9 , wherein the second connection point of the first memory element is the free layer of the first MTJ stack, and the first connection point of the second memory element is the pinned layer of the second MTJ stack.