Memory initialization reporting and control

1. A system, comprising:

a memory module including a memory with at least one memory chip;

a memory controller coupled to the memory; and

a bus interface circuit coupled to the memory controller and configured to send and receive data on an external bus,

the memory controller configured to:

in response to an initialization process of the memory module, initialize a status register with an initial ready time value and a memory readiness status;

conduct a memory readiness test on the memory;

while conducting the memory readiness test, estimate a new ready time based on a current rate of completion of the memory readiness test;

update the ready time value in the status register based on the new ready time; and

after finishing the memory readiness test, update the memory readiness status in the status register; and

a processor coupled to the bus and configured to:

access the status register through the bus;

determine a current ready time value; and

check for results of the memory readiness test.

2. The system of claim 1 , wherein the memory readiness test is part of a power on self test (POST) process.

3. The system of claim 1 , wherein the processor repeatedly accesses the status register to determine if the current ready time value has changed.

4. The system of claim 1 , wherein the memory controller receives and responds to memory requests according to a Cache Coherent Interconnect for Accelerators (CCIX) standard.

5. The system of claim 1 , wherein the memory includes volatile memory and non-volatile memory.

6. The system of claim 1 , wherein the memory controller is configured to selectively set the new ready time to be greater than an original ready time indicated by the initial ready time value.

7. The system of claim 1 , wherein the memory controller is configured to selectively set the new ready time to be less than an original ready time indicated by the initial ready time value.

8. A memory module, comprising:

a memory including at least one memory chip;

a memory controller coupled to the memory;

a bus adapter coupled to the memory controller and configured to send and receive data on an external bus;

the memory controller configured to:

in response to an initialization process of the memory module, initialize a status register with a ready time value and a memory readiness status;

enable the status register to be accessed through the bus;

conduct a memory readiness test on the memory;

while conducting the memory readiness test, estimate a new ready time based on a current rate of completion of the memory readiness test;

update the ready time value in the status register based on the new ready time; and

upon finishing the memory readiness test, update the memory readiness status in the status register.

9. The memory module of claim 8 , wherein the memory readiness test is part of a power on self test (POST) process.

10. The memory module of claim 8 , wherein the memory controller receives and responds to memory requests according to a Cache Coherent Interconnect for Accelerators (CCIX) standard.

11. The memory module of claim 8 , wherein the memory includes volatile memory and non-volatile memory.

12. The memory module of claim 8 , wherein the memory controller is configured to selectively set the new ready time to be greater than an original ready time indicated by the initial ready time value.

13. The memory module of claim 8 , wherein the memory controller is configured to selectively set the new ready time to be less than an original ready time indicated by the initial ready time value.

14. A method, comprising:

in response to an initialization process at a memory module, initializing a status register with an initial ready time value and a memory readiness status;

conducting a memory readiness test on the memory module;

while conducting the memory readiness test, estimating a new ready time based on a current rate of completion of the memory readiness test;

updating the ready time value in the status register based on the new ready time;

providing access to the new ready time value over an external bus; and

after finishing the memory readiness test, updating the memory readiness status in the status register.

15. The method of claim 14 , wherein the memory readiness test is part of a power on self test (POST) process.

16. The method of claim 14 , further comprising repeatedly accessing the status register over the external bus to determine if the current ready time value has changed.

17. The method of claim 14 , wherein the memory module includes volatile memory and non-volatile memory.

18. The method of claim 14 , further comprising selectively setting the new ready time to be greater than an original ready time indicated by the initial ready time value.

19. The method of claim 14 , further comprising selectively setting the new ready time to be less than an original ready time indicated by the initial ready time value.

20. A memory module, comprising:

a memory including at least one memory chip;

a memory controller coupled to the memory;

a bus adapter coupled to the memory controller and configured to send and receive data on an external bus;

the memory controller configured to:

in response to an initialization process of the memory module, initialize a status register with memory readiness status and a ready time value indicating an expected amount of time to conduct a memory readiness test;

enable and perform at least one access of the status register through the bus;

conduct the memory readiness test on the memory; and

upon finishing the memory readiness test, update the memory readiness status in the status register.

21. The memory module of claim 20 , wherein the memory readiness test is part of a power on self test (POST).

22. The memory module of claim 20 , wherein the memory controller receives and responds to memory requests according to a Cache Coherent Interconnect for Accelerators (CCIX) standard.

23. The memory module of claim 20 , wherein the memory includes volatile memory and non-volatile memory.