IP Library › Granted Patent US 10,964,597
Granted Patent B2
US 10,964,597 · App. 16/567,047 · Granted Mar 30, 2021

Element chip manufacturing method

Inventors: Atsushi Harikai (Osaka, JP); Shogo Okita (Hyogo, JP); Noriyuki Matsubara (Yamanashi, JP); Hidefumi Saeki (Osaka, JP); Akihiro Itou (Kyoto, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L21/78H01L21/6836
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,964,597
App. No.
16/567,047
Granted
Mar 30, 2021
Kind
B2
Abstract

An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.

Claims (17)

1. An element chip manufacturing method comprising:

a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet;

a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier, the second conveying carrier being able to be conveyed together with the first conveying carrier;

a preprocessing step of preprocessing the substrate, after the placing step;

a removing step of removing the second conveying carrier, after the preprocessing step; and

a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.

2. The element chip manufacturing method of claim 1 , wherein

the substrate is provided with a plurality of element regions, and a dicing region defining the element regions, and has a third surface not facing the first surface of the holding sheet, and a fourth surface opposite the third surface, and

the preprocessing step includes at least one of:

a coating step of coating the third surface of the substrate held on the holding sheet with a raw material of a protective film,

a curing step of curing the raw material, to form the protective film on the third surface, and

a patterning step of forming an aperture in the protective film, to expose the substrate along the dicing region.

3. The element chip manufacturing method of claim 1 , wherein the second conveying carrier supports the substrate, with the holding sheet interposed between the second conveying carrier and the substrate.

4. The element chip manufacturing method of claim 3 , wherein a portion of the second conveying carrier, the portion being in contact with the holding sheet, has a rough surface.

5. The element chip manufacturing method of claim 3 , wherein a portion of the second conveying carrier, the portion being in contact with the holding sheet, has electrical conductivity.

6. The element chip manufacturing method of claim 1 , wherein the second conveying carrier is an annular body, and supports the frame.

7. The element chip manufacturing method of claim 1 , wherein the second conveying carrier has a first portion rising so as to surround a circumference of the frame.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2021
From: HARIKAI, ATSUSHI; OKITA, SHOGO; MATSUBARA, NORIYUKI; SAEKI, HIDEFUMI; ITOU, AKIHIRO
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 055071/0406 →
Priority Claims (1)
JP JP2018-179071 · Sep 25, 2018 · national
Continuity (1)
Related Publication 20200098636A1 · Mar 26, 2020