Semiconductor structure
A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures.
1. A semiconductor structure, comprising:
a substrate comprising a resistor region and a dense region and having isolation structures and dummy support patterns located in the resistor region, wherein each of the isolation structures is located between two adjacent dummy support patterns;
dummy conductive structures, wherein each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides;
resistor elements disposed above the dummy conductive structures and aligned with the dummy conductive structures, wherein the resistor elements are separated from the dummy conductive structures, and a width of each of the resistor elements is equal to a width of each of the dummy conductive structures; and
at least one conductive structure disposed on the substrate in the dense region, wherein the at least one conductive structure in the dense region and the dummy conductive structures in the resistor region have the same width.
2. The semiconductor structure of claim 1 , wherein the dummy support patterns are a portion of the substrate.
3. The semiconductor structure of claim 1 , wherein a width of a top portion of each of the dummy support patterns is less than a distance between two adjacent dummy conductive structures.
4. The semiconductor structure of claim 1 , wherein each of the dummy support patterns is located at a central location between two adjacent dummy conductive structures.
5. The semiconductor structure of claim 1 , wherein a width of a top portion of each of the isolation structures is greater than the width of each of the dummy conductive structures.
6. The semiconductor structure of claim 1 , wherein the dummy conductive structures comprise dummy metal gate structures or dummy contacts.
7. The semiconductor structure of claim 1 , wherein each of the dummy conductive structures is located at a central location of each of the isolation structures.
8. The semiconductor structure of claim 1 , wherein the dense region is located at one side or two sides of the resistor region.
9. The semiconductor structure of claim 8 , wherein the isolation structures are further disposed in the substrate in the dense region.
10. The semiconductor structure of claim 9 , further comprising at least one active region located between two adjacent isolation structures in the dense region.
11. The semiconductor structure of claim 9 , wherein the at least one conductive structure is disposed between two adjacent isolation structures.
12. The semiconductor structure of claim 11 , wherein the at least one conductive structure comprises a metal gate structure.
13. The semiconductor structure of claim 1 , wherein the resistor elements comprise high-resistance resistors.
14. The semiconductor structure of claim 1 , wherein the resistor region has no contact disposed in a dielectric layer.
15. The semiconductor structure of claim 1 , wherein the resistor elements are embedded and suspended within a dielectric layer.
16. The semiconductor structure of claim 1 , wherein an empty area and one of the dummy support patterns are disposed between adjacent dummy conductive structures configured along an extending direction of the dummy conductive structures, respectively.
17. The semiconductor structure of claim 1 , wherein the resistor region has no contact disposed in a dielectric layer, and the resistor elements are embedded and suspended within the dielectric layer.