Cryogenic semiconductor device having buried channel array transistor
A cryogenic semiconductor device includes isolation regions defining an active region having a first P-type ion concentration in a substrate, a gate structure in the substrate, and an ion implantation region having a second P-type ion concentration in the active region below the gate structure, wherein the gate structure includes a gate dielectric layer conformally disposed on inner sidewalls of a gate trench, a lower gate electrode disposed on the gate dielectric layer, and an upper gate electrode disposed on the lower gate electrode, wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.
1. A cryogenic semiconductor device comprising:
isolation regions defining an active region having a first P-type ion concentration in a substrate;
a gate structure disposed in the substrate; and
an ion implantation region having a second P-type ion concentration in the active region below the gate structure to increase a threshold voltage of a channel region of the gate structure,
wherein the gate structure comprises:
a gate dielectric layer conformally disposed on inner sidewalls of a gate trench;
a lower gate electrode directly disposed on the gate dielectric layer, and an upper gate electrode directly disposed on the lower gate electrode,
wherein:
the lower gate electrode has a relatively lower work function than the upper gate electrode,
the lower gate electrode includes polysilicon doped with an N-type ion for lowering the threshold voltage of the channel region of the gate structure,
the upper gate electrode includes titanium nitride, and
the lower gate electrode has a relatively higher resistance than the upper gate electrode.
2. The cryogenic semiconductor device of claim 1 , wherein the lower gate electrode is conformally disposed on the gate dielectric layer in a lining shape.
3. The cryogenic semiconductor device of claim 1 , wherein the upper gate electrode fills the gate trench and has a rail-like shape,
wherein side surfaces of the upper gate electrode are directly surrounded by the gate dielectric layer.
4. The cryogenic semiconductor device of claim 1 , further comprising a capping gate electrode covering an upper surface of the upper gate electrode,
wherein the capping gate electrode is a conductor and portions of side surfaces of the gate capping layer are directly surrounded by the gate dielectric layer.
5. The cryogenic semiconductor device of claim 4 , wherein the capping gate electrode includes a lower capping gate electrode and an upper capping gate electrode disposed on the lower capping gate electrode.
6. The cryogenic semiconductor device of claim 5 , wherein the lower capping gate electrode includes a barrier metal, and the upper capping gate electrode includes polysilicon doped with an N-type ion.
7. A cryogenic semiconductor device comprising:
isolation regions defining an active region in a substrate;
a gate structure disposed in the substrate; and
an ion implantation region in the active region below the gate structure to increase a threshold voltage of a channel region of the gate structure,
wherein the gate structure comprises:
a gate dielectric layer conformally disposed on inner sidewalls of a gate trench; and
a lower gate electrode directly disposed on the gate dielectric layer; an intermediate gate electrode directly disposed on the lower gate electrode and an upper gate electrode directly disposed on the intermediate gate electrode,
wherein the lower gate electrode has a relatively lower work function than the intermediate gate electrode,
the intermediate gate electrode has a relatively lower work function than the upper gate electrode, and
the lower gate electrode has a relatively higher resistance than the intermediate gate electrode,
the intermediate gate electrode has a relatively higher resistance than the upper gate electrode,
the lower gate electrode includes polysilicon doped with an N-type ion for lowering the threshold voltage of the channel region of the gate structure,
the intermediate gate electrode includes titanium nitride, and
wherein the upper gate electrode includes a metal.
8. The cryogenic semiconductor device of claim 7 , wherein the active region has a relatively low P-type ion concentration, and the ion implantation region has a relatively high P-type ion concentration.
9. The cryogenic semiconductor device of claim 7 , wherein the lower gate electrode is conformally disposed to surround a bottom surface and side surfaces of the intermediate gate electrode in a lining shape.
10. The cryogenic semiconductor device of claim 9 , wherein the intermediate gate electrode is conformally disposed to surround a bottom surface and side surfaces of the upper gate electrode in a lining shape.
11. The cryogenic semiconductor device of claim 7 , further comprising an upper capping gate electrode covering an upper surface of the upper gate electrode,
wherein the upper capping gate electrode and the lower gate electrode include a same material.
12. The cryogenic semiconductor device of claim 11 , further comprising a lower capping gate electrode disposed between the upper surface of the upper gate electrode and the upper capping gate electrode,
wherein the lower capping gate electrode includes the same material as the intermediate gate electrode.
13. A cryogenic semiconductor device comprising:
isolation regions defining an active region having a first P-type ion concentration in a substrate;
a gate structure disposed in the substrate; and
an ion implantation region having a second P-type ion concentration in the active region below the gate structure, wherein the ion implantation region increases a threshold voltage of a channel region of the gate structure,
wherein the gate structure comprises:
a gate dielectric layer conformally disposed on inner sidewalls of a gate trench; and
a lower gate electrode directly disposed on the gate dielectric layer;
an upper gate electrode disposed on the lower gate electrode; and
a capping gate electrode disposed on the upper gate electrode,
wherein the lower gate electrode, the upper gate electrode, and the capping gate electrode are conductors.
14. The cryogenic semiconductor device of claim 13 , wherein:
the lower gate electrode includes polysilicon doped with and N-type ion, and
the upper gate electrode includes one of a metal, a metal alloy, or a metal compound.
15. The cryogenic semiconductor device of claim 13 , wherein the capping gate electrode includes polysilicon doped with an N-type ion.
16. The cryogenic semiconductor device of claim 13 ,
wherein the capping gate electrode includes a lower capping gate electrode on the upper gate electrode and an upper capping gate electrode on the lower capping gate electrode.
17. The cryogenic semiconductor device of claim 13 , wherein:
the lower capping gate electrode includes polysilicon doped with an N-type ion, and
the upper capping gate electrode includes a barrier metal.
18. The cryogenic semiconductor device of claim 13 , further comprising an intermediate gate electrode between the lower gate electrode and the upper gate electrode, wherein the intermediate gate electrode includes a barrier metal and the upper gate electrode includes a metal.
19. The cryogenic semiconductor device of claim 13 , wherein:
the lower gate electrode decreases the threshold voltage of the channel region of the gate structure.
20. The cryogenic semiconductor device of claim 13 , wherein:
the lower gate electrode and the capping gate electrode have relatively higher resistance and work functions the than the upper gate electrode.