On-time timer circuit with external clock for switching converter control
A switching converter controller includes an on-time timer circuit coupled to a switch driver circuit. The on-time timer circuit includes an up/down counter with a clock input node. The on-time timer circuit also includes a latch with an input coupled to an external clock signal and with an output coupled to the clock input node. The on-time timer circuit also includes an on-time capacitor array with a control terminal coupled an output of the up/down counter.
1. An electrical system, comprising:
a battery configured to provide an input supply voltage;
a switching converter coupled to the battery, the switching converter includes a power switch;
a load coupled to an output of the switching converter;
a control circuit coupled to the power switch, the control circuit including:
a switch driver circuit coupled to the power switch;
a summing comparator circuit configured to output a first control signal that indicates when to turn the power switch on; and
an on-time timer circuit configured to output a second control signal separate from the first control signal, the second control signal is based on a latched external clock signal, the on-time timer circuit including a delay circuit, and the latch includes a D flip flop having:
a data input node;
a clock input node coupled to an output of the delay circuit; and
a reset input node,
the data input node is configured to receive a low-side switch blanking time completion signal, and
the external clock signal is coupled to an input of the delay circuit and to the reset input node.
2. The electrical system of claim 1 , in which the on-time timer circuit includes an up/down counter and a latch, an output of the latch is coupled to a clock input of the up/down counter.
3. The electrical system of claim 2 in which the on-time timer circuit includes an OR gate with an output coupled to the data input node, the OR gate is configured to receive the low-side switch blanking time completion signal and a discontinuous conduction mode (DCM) signal as inputs.
4. The electrical system of claim 2 , in which the latch includes a D flip flop having:
a data input node;
a clock input node; and
a reset input node,
the data input node and the reset input node are configured to receive the external clock signal, and
the clock input node is configured to receive a low-side switch blanking time completion signal.
5. The electrical system of claim 2 , in which the on-time timer circuit includes:
a comparator; and
an on-time capacitor array with a control terminal, a first terminal, and a second terminal, the control terminal is coupled to an output of the up/down counter, the first terminal is coupled to an input of the comparator, and the second terminal is coupled to a ground node.
6. The electrical system of claim 1 , in which the external clock is provided by an external source independent of a switching frequency of the switching converter.
7. A switching converter, comprising:
a power switch;
a control circuit coupled to the power switch, the control circuit including:
a switch driver circuit;
a summing comparator circuit coupled to the switch driver circuit;
an on-time timer circuit coupled to the switch driver circuit, the on-time timer circuit including:
an up/down counter with a clock input node;
a latch with an input coupled to an external clock signal and with an output coupled to the clock input node; and
an on-time capacitor array with a control terminal coupled an output of the up/down counter.
8. The switching converter of claim 7 , in which the on-time timer circuit includes a delay circuit, and the latch including a D flip flop having:
a data input node;
a clock input node coupled to an output of the delay circuit; and
a reset input node,
the data input node is configured to receive a low-side switch blanking time completion signal, and
the external clock signal is coupled to an input of the delay circuit and to the reset input node.
9. The switching converter of claim 8 , in which the on-time timer circuit includes an OR gate with an output coupled to the data input node, the OR gate is configured to receive the low-side switch blanking time completion signal and a discontinuous conduction mode (DCM) signal as inputs.
10. The switching converter of claim 7 , in which the latch includes a D flip flop having:
a data input node;
a clock input node; and
a reset input node,
the data input node and the reset input node are configured to receive the external clock signal, and
the clock input node of the D flip flop is configured to receive a low-side switch blanking time completion signal.
11. The switching converter of claim 7 , in which the external clock signal is provided by an external source independent of a switching frequency of the switching converter.
12. The switching converter of claim 7 , including an AND gate, a first input node of the AND gate is coupled to an output of the summing comparator circuit, and a second input node of the AND gate is coupled to a minimum off-time control signal.
13. The switching converter of claim 12 , in which the switch driver circuit includes an SR latch, a set input node of the SR latch is coupled to an output of the AND gate, a reset input node of the SR latch is coupled to an output of an OR gate, and an output of the on-time timer circuit is input to the OR gate.
14. The switching converter of claim 13 , in which the OR gate is configured to receive a maximum on-time control signal as an input.
15. A switching converter controller, comprising:
an on-time timer circuit; and
a switch driver circuit coupled to the on-time timer circuit, the on-time timer circuit including:
an up/down counter with a clock input node;
a latch with an input coupled to an external clock signal and with an output coupled to the clock input node; and
an on-time capacitor array with a control terminal coupled an output of the up/down counter.
16. The switching converter controller of claim 15 , in which the on-time timer circuit includes a delay circuit, and the latch including a D flip flop having:
a data input node;
a clock input node coupled to an output of the delay circuit; and
a reset input node,
the data input node is configured to receive a low-side switch blanking time completion signal, and
the external clock signal is coupled to an input of the delay circuit and to the reset input node.
17. The switching converter controller of claim 16 , in which the on-time timer circuit includes an OR gate with an output coupled to the data input node, the OR gate is configured to receive the low-side switch blanking time completion signal and a discontinuous conduction mode (DCM) signal as inputs.
18. The switching converter controller of claim 15 , in which the latch includes a D flip flop having:
a data input node;
a clock input node; and
a reset input node,
the data input node and the reset input node are configured to receive the external clock signal, and
the clock input node of the D flip flop is configured to receive a low-side switch blanking time completion signal.
19. The switching converter controller of claim 15 , in which the external clock signal is provided by an external source independent of a switching frequency of the switching converter.