Cell structures and semiconductor devices having same

1. A semiconductor device comprising:

fins formed on a substrate and arranged substantially parallel to a first direction;

the fins being organized into instances of a first row and instances of a second row, the first and second rows extending in the first direction;

each instance of the first row including a first predetermined number of fins having a first conductivity type; and

each instance of the second row including a second predetermined number of fins having a second conductivity type;

gate structures formed over corresponding ones of the fins and arranged substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction; and

a first structure having an odd number of contiguous rows including:

an even number of instances of the first row; and

an odd number of instances of the second row.

2. The semiconductor device of claim 1 , wherein:

each of the even number of instances of the first row in the first structure has a first width in the first direction; and

each of the odd number of instances of the second row in the first structure has a second width in the first direction, the second width being substantially different than the first width.

3. The semiconductor device of claim 1 , wherein:

a size in the first direction of each row is substantially the same.

4. A semiconductor device comprising:

active areas formed as predetermined shapes on a substrate and arranged relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions, the active areas comprising fingers, wherein each finger defines a long axis that extends in the first direction;

the active areas being organized into instances of a first row having a first conductivity and instances of a second row having a second conductivity, the first and second rows extending in the first direction;

each instance of the first row and of the second row including a corresponding first and second number predetermined number of the first tracks; and

a structure having at least two contiguous rows including:

at least one instance of the first row; and

at least one instance of the second row;

wherein:

each of the at least one instance of the first row in the structure has one or more of the fingers, each of the one or more of the fingers in the first row having a first width in the first direction; and

each of the at least one instance of the second row in the structure has one or more of the fingers, each of the one or more of the fingers in the second row having a second width in the first direction, the second width being substantially different than the first width.

5. The semiconductor device of claim 4 , wherein:

the structure has two contiguous rows.

6. The semiconductor device of claim 4 , wherein:

the second width is substantially twice the first width.

7. The semiconductor device of claim 4 , wherein one of the following is true:

the structure has an odd number of contiguous rows including:

an even number of instances of the first row; and

an odd number of instances of the second row; or

the structure has an even number of contiguous rows including:

at least one instance of the first row; and

at least one instance of the second row.

8. The semiconductor device of claim 7 , wherein one of the following is true:

in the structure which has the odd number of contiguous rows, at least two of the even number of one or more instances of the first row are contiguous; or

the structure which has the even number of contiguous rows includes:

at least two instances of the first row; and

at least two instances of the second row; and

wherein, in the structure which has the even number of contiguous rows, two or more of the at least two instances of the first row are contiguous.

9. The semiconductor device of claim 4 , wherein:

a perimeter of the structure is L-shaped.

10. The semiconductor device of claim 4 , wherein:

a perimeter of the structure is T-shaped.

11. The semiconductor device of claim 4 , wherein:

the active areas are configured for finFET technology.

12. A method of generating layout, the layout being stored on a non-transitory computer-readable medium, the method comprising:

generating active area patterns including:

configuring the active area patterns as predetermined shapes;

arranging the active area patterns relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions;

configuring the active area patterns into instances of a first row having a first conductivity and instances of a second row having a second conductivity, the first and second rows extending in the first direction, the active area patterns comprising finger patterns, wherein each finger pattern defines a long axis that extends in the first direction; and

configuring each instance of the first row and of the second row to include a predetermined number of the first tracks; and

defining a cell structure as having a place-and-route (PR) boundary which contains at least two contiguous rows including:

at least one instance of the first row having one or more of the finger patterns, each of the one or more of the finger patterns in the first row having a first width in the first direction; and

at least one instance of the second row having one or more of the finger patterns, each of the one or more of the finger patterns in the second row having a second width in the first direction;

setting the first width to be substantially different than the second width.

13. The method of claim 12 , wherein:

the at least one instance of the first row in the cell structure has a first width in the first direction; and

the at least one instance of the second row in the cell structure has a second width in the first direction;

the method further comprising:

setting the second width to be substantially twice as large as the first width.

14. The method of claim 12 , wherein the defining the cell structure includes:

defining the cell structure such that the PR boundary contains an odd number of contiguous rows including:

an even number of instances of the first row; and

an odd number of instances of the second row.

15. The method of claim 14 , wherein the defining the cell structure includes:

locating the even number of instances of the first row in the cell structure so as to be contiguous.

16. The method of claim 12 , wherein the defining the cell structure includes:

defining the cell structure such that the PR boundary contains an even number of contiguous rows including:

at least one instance of the first row; and

at least one instance of the second row.

17. The method of claim 16 , wherein the defining the cell structure further includes:

defining the cell structure such that the PR boundary contains the even number of contiguous rows including:

at least two instances of the first row; and

at least two instances of the second row; and

configuring either the at least two instances of the first row or the at least two instances of the second row to be contiguous.

18. The method of claim 12 , wherein the defining the cell structure includes:

configuring a periphery of the cell structure to be L-shaped; or

configuring the periphery of the cell structure to be T-shaped.

19. The method of claim 12 , wherein:

the generating the active area patterns includes:

configuring the active area patterns for finFET technology.

20. The method of claim 12 , further comprising:

fabricating, based on the layout, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an inchoate semiconductor integrated circuit.