Shift register and method for driving the same, gate driving circuit, and display device

1. A shift register, comprising:

an output sub-circuit coupled to a pull-up node, a clock signal terminal and a signal output terminal, wherein the output sub-circuit is configured to transmit a voltage of the clock signal terminal to the signal output terminal under control of a voltage of the pull-up node; and

a compensation sub-circuit coupled to the pull-up node, the clock signal terminal and the signal output terminal, wherein the compensation sub-circuit is configured to transmit a voltage of the signal output terminal to the pull-up node under control of the voltage of the pull-up node and the voltage of the clock signal terminal.

2. The shift register according to claim 1 , wherein the compensation sub-circuit includes:

a first compensation sub-circuit coupled to the pull-up node and the clock signal terminal; and

a second compensation sub-circuit coupled to the pull-up node, the signal output terminal and the first compensation sub-circuit, wherein

the first compensation sub-circuit is configured to transmit the voltage of the clock signal terminal to the second compensation sub-circuit under control of the voltage of the pull-up node, and

the second compensation sub-circuit is configured to transmit the voltage of the signal output terminal to the pull-up node under control of the received voltage of the clock signal terminal.

3. The shift register according to claim 2 , wherein

the first compensation sub-circuit includes:

a first transistor, wherein a control electrode of the first transistor is coupled to the pull-up node, and a first electrode of the first transistor is coupled to the clock signal terminal; and

the second compensation sub-circuit includes:

a second transistor, wherein a control electrode of the second transistor is coupled to a second electrode of the first transistor, a first electrode of the second transistor is coupled to the signal output terminal, and a second electrode of the second transistor is coupled to the pull-up node.

4. The shift register according to claim 1 , wherein the output sub-circuit includes a scan output sub-circuit and a cascade output sub-circuit; wherein

the scan output sub-circuit is configured to transmit the voltage of the clock signal terminal as a scan signal to a scan signal output terminal under control of the voltage of the pull-up node, and the cascade output sub-circuit is configured to transmit the voltage of the clock signal terminal as a cascade signal to a cascade signal output terminal under control of the voltage of the pull-up node; and

the signal output terminal is one of the scan signal output terminal and the cascade signal output terminal.

5. The shift register according to claim 4 , wherein the signal output terminal is the cascade signal output terminal.

6. The shift register according to claim 4 , wherein

the scan output sub-circuit includes:

a third transistor, wherein a control electrode of the third transistor is coupled to the pull-up node, a first electrode of the third transistor is coupled to the clock signal terminal, and a second electrode of the third transistor is coupled to the scan signal output terminal; and

a first capacitor, wherein a first electrode of the first capacitor is coupled to the pull-up node, and a second electrode of the first capacitor is coupled to the scan signal output terminal; and

the cascade output sub-circuit includes:

a fourth transistor, wherein a control electrode of the fourth transistor is coupled to the pull-up node, a first electrode of the fourth transistor is coupled to the clock signal terminal, and a second electrode of the fourth transistor is coupled to the cascade signal output terminal.

7. The shift register according to claim 4 , further comprising:

a first pull-down sub-circuit coupled to the scan signal output terminal, a third voltage terminal and a pull-down node, wherein the first pull-down sub-circuit is configured to transmit a voltage received at the third voltage terminal to the scan signal output terminal under control of a voltage of the pull-down node; and

a second pull-down sub-circuit coupled to the cascade signal output terminal, a first voltage terminal and the pull-down node, wherein the second pull-down sub-circuit is configured to transmit a voltage received at the first voltage terminal to the cascade signal output terminal under control of the voltage of the pull-down node.

8. The shift register according to claim 7 , wherein

the first pull-down sub-circuit includes:

a ninth transistor, wherein a control electrode of the ninth transistor is coupled to the pull-down node, a first electrode of the ninth transistor is coupled to the third voltage terminal, and a second electrode of the ninth transistor is coupled to the scan signal output terminal; and

the second pull-down sub-circuit includes:

a tenth transistor, wherein a control electrode of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the first voltage terminal, and a second electrode of the tenth transistor is coupled to the cascade signal output terminal.

9. The shift register according to claim 1 , further comprising: a first control sub-circuit coupled to a first voltage terminal, a second voltage terminal, the pull-up node and a pull-down node, wherein

the first control sub-circuit is configured to transmit a voltage received at the first voltage terminal to the pull-down node under control of the voltage of the pull-up node, and to transmit a voltage received at the second voltage terminal to the pull-down node under control of the voltage of the pull-up node and the voltage received at the second voltage terminal.

10. The shift register according to claim 9 , wherein the first control sub-circuit includes:

a fifth transistor, wherein a control electrode of the fifth transistor is coupled to a control node, a first electrode of the fifth transistor is coupled to the second voltage terminal, and a second electrode of the fifth transistor is coupled to the pull-down node;

a sixth transistor, wherein a control electrode of the sixth transistor is coupled to the pull-up node, a first electrode of the sixth transistor is coupled to the first voltage terminal, and a second electrode of the sixth transistor is coupled to the pull-down node;

a seventh transistor, wherein a control electrode of the seventh transistor is coupled to the pull-up node, a first electrode of the seventh transistor is coupled to the first voltage terminal, and a second electrode of the seventh transistor is coupled to the control node; and

an eighth transistor, wherein a control electrode and a first electrode of the eighth transistor are coupled to the second voltage terminal, and a second electrode of the eighth transistor is coupled to the control node.

11. The shift register according to claim 1 , further comprising: a second control sub-circuit coupled to a first voltage terminal, the pull-up node and a pull-down node, wherein

the second control sub-circuit is configured to transmit a voltage received at the first voltage terminal to the pull-up node under control of a voltage of the pull-down node.

12. The shift register according to claim 11 , wherein the second control sub-circuit includes:

an eleventh transistor, wherein a control electrode of the eleventh transistor is coupled to the pull-down node, a first electrode of the eleventh transistor is coupled to the first voltage terminal, and a second electrode of the eleventh transistor is coupled to the pull-up node.

13. The shift register according to claim 1 , further comprising:

an input sub-circuit coupled to a signal input terminal and the pull-up node, wherein the input sub-circuit is configured to transmit a voltage of the signal input terminal to the pull-up node under control of the voltage of the first signal input terminal; and

a reset sub-circuit coupled to a reset signal terminal, a first voltage terminal and the pull-up node, and the reset sub-circuit is configured to transmit a voltage received at the first voltage terminal to the pull-up node under control of a voltage of the reset signal terminal.

14. The shift register according to claim 13 , wherein

the input sub-circuit includes:

a twelfth transistor, wherein a control electrode and a first electrode of the twelfth transistor are coupled to the signal input terminal, and a second electrode of the twelfth transistor is coupled to the pull-up node; and

the reset sub-circuit includes:

a thirteenth transistor, wherein a control electrode of the thirteenth transistor is coupled to the reset signal terminal, a first electrode of the thirteenth transistor is coupled to the first voltage terminal, and a second electrode of the thirteenth transistor is coupled to the pull-up node.

15. The shift register according to claim 1 , further comprising: an initialization sub-circuit coupled to an initialization signal terminal, the pull-up node and a first voltage terminal, wherein

the initialization sub-circuit is configured to transmit a voltage received at the first voltage terminal to the pull-up node under control of a voltage of the initialization signal terminal.

16. The shift register according to claim 15 , wherein the initialization sub-circuit includes:

a fourteenth transistor, wherein a control electrode of the fourteenth transistor is coupled to the initialization signal terminal, a first electrode of the fourteenth transistor is coupled to the first voltage terminal, and a second electrode of the fourteenth transistor is coupled to the pull-up node.

17. A gate driving circuit, comprising a plurality of cascaded shift registers according to claim 1 .

18. A display device, comprising the gate driving circuit according to claim 17 .

19. A method for driving the shift register according to claim 1 , comprising:

turning on the output sub-circuit under control of the voltage of the pull-up node, and transmitting, by the output sub-circuit, the voltage of the clock signal terminal to the signal output terminal; and

turning on the compensation sub-circuit under control of the voltage of the pull-up node and the voltage of the clock signal terminal, and transmitting, by the compensation sub-circuit, the voltage of the signal output terminal to the pull-up node to compensate the voltage of the pull-up node.