Mask-integrated surface protective tape
A mask-integrated surface protective tape for production of semiconductor chips, with the production containing steps (a) to (d), which tape comprises a base film and a mask material layer provided thereon, wherein a wetting tension of the base film on the side from which the mask material layer has been peeled is from 20.0 mN/m to 48.0 mN/m, and wherein a surface roughness Ra of the base film on the side from which the mask material layer has been peeled is within a range from 0.05 μm to 2.0 μm when measured in conformity to JIS B0601, (a) a specific laminating step; (b) a specific peeling step; (c) a specific plasma-dicing step; and (d) a specific ashing step.
1. A process for producing semiconductor chips using a mask-integrated surface protective tape, wherein the mask-integrated surface protective tape comprises a base film and a mask material layer on the base film, said process comprising:
(a) a step of, in a state of having laminated the mask-integrated surface protective tape on a side of a patterned surface of a semiconductor wafer, grinding a backing-face side of the semiconductor wafer; laminating a water fixing tape on the backing-face side of the semiconductor wafer; and supporting and fixing the semiconductor wafer to a ring flame;
(b) a step of, after peeling the base film of the mask-integrated surface protective tape, thereby exposing the mask material layer on top, forming an opening of a street of the semiconductor water by cutting a portion of the mask material layer corresponding to the street of the semiconductor wafer by laser;
(c) a plasma-dicing step of segmentalizing the semiconductor wafer on the street by a SF 6 plasma, thereby singulating the semiconductor wafer into semiconductor chips; and
(d) an ashing step of removing the mask material layer by an O 2 plasma,
wherein a wetting tension of the base film on a side from which the mask material layer is peeled is 20.0 mN/m or more and 48.0 mN/m or less, and wherein a surface roughness Ra of the base film on the side from which the mask material layer is peeled is within a range of 0.05 μm or more and 2.0 μm or less when measured in conformity to JIS B0601.
2. The process for producing semiconductor chips according to claim 1 , wherein an unevenness on the patterned surface of the semiconductor wafer on which the mask-integrated surface protective tape is laminated is 10 μm or more.