IP Library › Granted Patent US 10,971,412
Granted Patent B2
US 10,971,412 · App. 15/128,227 · Granted Apr 6, 2021

Mounting substrate and electronic apparatus

Inventors: Akiyoshi Aoyagi (Kanagawa, JP); Ken Kikuchi (Tokyo, JP); Katsuhiro Tomoda (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L22/22F21V19/003G09G3/32H01L25/0753H01L25/167H01L33/54H01L33/58H01L33/62F21Y2115/10G09G2300/0408G09G2300/0421H01L2924/0002
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Quick Facts
Patent No.
US 10,971,412
App. No.
15/128,227
Granted
Apr 6, 2021
Kind
B2
Abstract

A mounting substrate according to an embodiment of the present technology includes: a wiring substrate ( 30 ); a plurality of light-emitting elements ( 12 ) arranged in a matrix on the wiring substrate; and a plurality of drive ICs ( 13 ) that are arranged in a matrix on the wiring substrate, and control light emission of the light-emitting elements. The light-emitting elements and the drive ICs are mounted on a same surface. The wiring substrate includes a plurality of first wiring lines ( 16 ) on a mounting surface whre the light-emitting elements and the dive ICs are mounted. The first wiring lines electrically couple the light-emitting elements to the drive ICs.

Claims (37)

1. A mounting substrate, comprising:

a wiring substrate;

a plurality of light-emitting elements arranged in a matrix on a surface of the wiring substrate; and

a plurality of drive ICs that are arranged in a matrix on the surface of the wiring substrate, and control light emission of the light-emitting elements,

wherein the light-emitting elements are mounted in direct contact with a top surface of a seed layer formed on the wiring substrate and the drive ICs are mounted in direct contact with the top surface of the seed layer formed on the wiring substrate, and

the wiring substrate includes a plurality of first wiring lines on the surface where the light-emitting elements and the drive ICs are mounted, the first wiring lines electrically coupling the light-emitting elements to the drive ICs, wherein

the wiring substrate includes

a plurality of selection lines formed in a layer lower than the first wiring lines, and extending in a row direction,

a plurality of signal lines formed in a layer lower than the first wiring lines, and extending in a column direction,

one or a plurality of second wiring lines formed in the same layer as the first wiring lines or in a layer lower than the first wiring lines, and electrically coupled to each of the selection lines, and

one or a plurality of third wiring lines formed in the same layer as the first wiring lines or in a layer lower than the first wiring lines, and electrically coupled to each of the signal lines, and

the drive ICs are electrically coupled to the one or plurality of the second wiring lines and the one or plurality of the third wiring lines and wherein

the wiring substrate includes

a build-up substrate that includes a core substrate and one or more build-up layers formed on each of both sides of the core substrate, and in which interlayer electrical coupling is made by a via, and

a fine L/S (line and space) layer formed in contact with a top surface of the build-up substrate, wherein

an L/S of the fine L/S layer is smaller than an L/S of the build-up substrate,

the selection lines and the signal lines are formed in the build-up layer, and

the first wiring lines, the second wiring lines, and the third wiring lines are formed in the fine L/S layer.

2. The mounting substrate according to claim 1 , wherein the wiring substrate includes a resin layer that covers a surface including the light-emitting elements and the drive ICs.

3. An electronic apparatus provided with one or a plurality of mounting substrates and a control circuit that controls the one or plurality of mounting substrates, the mounting substrate comprising:

a wiring substrate;

a plurality of light-emitting elements arranged in a matrix on a surface of the wiring substrate; and

a plurality of drive ICs that are arranged in a matrix on the surface of the wiring substrate, and control light emission of the light-emitting elements,

wherein the light-emitting elements are mounted in direct contact with a top surface of a seed layer formed on the wiring substrate and the drive ICs are mounted in direct contact with the top surface of the seed layer formed on the wiring substrate, and

the wiring substrate includes a plurality of first wiring lines on the surface where the light-emitting elements and the drive ICs are mounted, the first wiring lines electrically coupling the light-emitting elements to the drive ICs, wherein

the wiring substrate includes

a plurality of selection lines formed in a layer lower than the first wiring lines, and extending in a row direction,

a plurality of signal lines formed in a layer lower than the first wiring lines, and extending in a column direction,

one or a plurality of second wiring lines formed in the same layer as the first wiring lines or in a layer lower than the first wiring lines, and electrically coupled to each of the selection lines, and

one or a plurality of third wiring lines formed in the same layer as the first wiring lines or in a layer lower than the first wiring lines, and electrically coupled to each of the signal lines, and

the drive ICs are electrically coupled to the one or plurality of the second wiring lines and the one or plurality of the third wiring lines and wherein

the wiring substrate includes

a build-up substrate that includes a core substrate and one or more build-up layers formed on each of both sides of the core substrate, and in which interlayer electrical coupling is made by a via, and

a fine L/S (line and space) layer formed in contact with a top surface of the build-up substrate, wherein

an L/S of the fine L/S layer is smaller than an L/S of the build-up substrate,

the selection lines and the signal lines are formed in the build-up layer, and

the first wiring lines, the second wiring lines, and the third wiring lines are formed in the fine L/S layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2017
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 043546/0060 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2016
From: AOYAGI, AKIYOSHI; KIKUCHI, KEN; TOMODA, KATSUHIRO
To: SONY CORPORATION
Reel/Frame 040232/0817 →
Priority Claims (1)
JP JP2014-074843 · Mar 31, 2014 · national
Continuity (1)
Related Publication 20170103926A1 · Apr 13, 2017
Cited By (2)
US 12,199,077 US 12,388,057